Hardware

Hardware 2D graphics engine — Additional functionality and better performance for FPGA-based 2D video controller

This project is to develop hardware accelerated 2D display controller boards for easily adding interactive user interfaces to single-purpose industrial and commercial machines.

Traditionally, to make stand-alone machines and systems (i.e. not based on PCs but on custom computing boards), if developers need to provide a high resolution graphical user interfaces (GUI) they are offered only two inconvenient options: use a complex system like a Linux-capable single board computer, or limit performance to low resolutions that are unsuitable for medium to large displays. The latter case simply prevents successfully marketing those products, while the former requires a high degree of qualifications in embedded systems development, where the requirements are simple products like signage systems or vending machines.

The controller boards (CPU and FPGA based, released as open hardware) are capable of loading previously stored images (lossy or lossless), plus movies, fonts and other resources required. The drawing commands are implemented with hardware acceleration on the FPGA board, using a custom C-to-hardware tool: CflexHDL, making it possible to use a fully open-source toolchain. Interactivity is achieved by the use of a USB host capable of handling mouse, keyboards and touchscreens. Displays of multiple kinds are supported by the use of PCB adapters, including: Analog VGA, DVI protocol (compatible with HDMI monitors), LVDS for direct connection to laptop replacement displays, among other options. The controllers can be used stand-alone (like a development platform) or be controlled by other systems like Arduino or similar boards.

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AALT (Accelerated Analog Layout Tool) — More efficient analog layout generation for chips)

AALT (Accelerated Analog Layout Tool) aims to increase the productivity of analog integrated circuit layout by keeping the human in the loop but automating the time consuming, monotonous activities. The tool will generate matched structures in guard rings and wells with DRC aware optimisation of sub-circuit block placement and simple auto-routing. The goal is to improve analog layout speed by 50% by letting the computer do the boring work and leave the human to do the thinking. It will support existing open-source projects KLayout and PDKMaster.

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Analog/Mixed-Signal Library — OSHW component library for ASIC design

One of the gaps in the open chip toolchain is a libre-licensed analog/mixed-signal library. Having access to such a library contributes to having a fully open ASIC design infrastructure through which secure and trustworthy open hardware can subsequently be built.

This project is trying to fill that void. The first part of the project consists of enhancing and stabilising the underlying PDKMaster project, and allow it to facilitate programmatic co-generation of circuit and layout with integrated support for circuit simulation. This should make resulting circuits DRC and LVS clean by design. Second part of the bootstrapping effort is then to implement a set of scalable analog/mixed-signal blocks which can be integrated into PDKMaster. The initial set will consist of the following 4 core blocks: a voltage reference, a PLL (phase-locked loop), a low frequency, low accuracy ADC and a low frequency, low accuracy DAC.

The overall focus is on proving the overall suitability of the PDKMaster framework, rather than on the complexity and difficulty of the individual analog/mixed-signal blocks which are to be added. Thanks to proper documentation and examples, users can start expanding the available building blocks by adding their own contributions.

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Apicula — Open source tools for working with Gowin FPGAs

Only a few years ago, you could only program FPGAs with the proprietary tools provided by the vendors, locking you into that ecosystem and its features and bugs. But open source FPGA tools have been making great strides, and there are now mature open source synthesis and PnR tools, namely Yosys and Nextpnr. However, only Lattice FPGAs are currently well supported, still de facto locking you into a single vendor. There are a few other projects, such as Apicula, that target other FPGAs, but none of them are feature complete and of production quality. The goal here is to take Apicula to the next level, where it goes from an experimental flow for FOSS enthusiasts to a production ready tool, finally and truly breaking FPGA vendor lock-in.

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Apicula IO primitives — Add additional IO primitives to libre Gowin FPGA tools

Apicula is a project that aims to provide open source tools to work with Gowin FPGAs. (FPGAs are repurposable chips used in many everyday and specialist electronic products for everything from tying systems together to highly specialized algorithm accelerators). In recent years open source FPGA tools have made great strides to break the vendor lock-in of commercial FPGA tools. But to completely break vendor lock-in a variety of mature toolchains are needed. We have reached a point of general usability, and with this grant Apicula aims to make another large leap forward, improving feature parity, documentation, and support for more advanced and specialized Gowin devices.

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ARMify — Auto-Identification of MCU Models to Simplify ARM Bare-Metal Reverse Engineering

ARMify aims to become a plugin for the open-source reverse engineering tool Ghidra, with its primary goal being to assist security analysts in analyzing ARM Cortex-M bare-metal firmware. This is achieved through automatic microcontroller model identification and annotation of memory-mapped peripherals. It helps analysts to understand how the firmware interacts with microcontroller features, offering significant time savings compared to manual cross-referencing with the microcontroller datasheet. The development entails creating an SVD parser (the SVD standard formalizes Cortex-M microcontroller system details, such as peripheral registers, in XML format) and a comprehensive microcontroller database, both of which will be released as standalone tools alongside ARMify. The SVD parser will enable the processing and preparation of Cortex-M microcontroller system details, while the microcontroller database will provide a repository of technical characteristics and a user-friendly interface for easy access.

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Balthazar — One laptop for the new internet age.

Project's ambition is to design and deliver an innovative and technically advanced open hardware (RISC-V/ISA) based, European made, inexpensive, FOSS laptop as a personal computing device, containing on board all desirable (FOSS compliant) hardware and software features and functionalities needed to prevent any 3rd party intrusion into the system. It adds physical safety features currently not available in the market such as hot-swappable CPU, hardwired switches for e.g. camera and audio devices, and a quickly removable encrypted hard drive and peripherals. A goal of Balthazar is to enable and educate end users to be private, safe and careful with their own data, and that of others. Another goal is to make computing more sustainable and reach eco-friendly footprint, by empowering users to take up their 'right to repair', through a modular laptop that allows components to be easily exchanged and upgraded - up to the CPU itself. The goal is to lead by example and gently lead other hardware manufacturers to become fully open and transparent. And create an educational platform, as well as an advanced computing device where its users (including those with low income ) to feel secure, safe and comfortable using it. For the children of all ages.

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Balthazar Casing — Open hardware laptop

Balthazar is a project that aims to create an advanced, open-hardware laptop that is affordable and accessible to everyone, while also being well-designed and ergonomic. The laptop will feature a range of hardware and software features designed to protect users' data and prevent third-party intrusion. It will also include physical safety features such as a hot-swappable CPU and hard-wired switches, as well as the ability for users to add external modules based on various instruction sets and systems on the module, as well as spare keyboards. The project's goals include empowering users to take control of their own data, making computing more sustainable through the use of modular components, and creating an educational platform and advanced computing device that is accessible to users of all income levels.

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Balthazar - One laptop for the new internet age. — A secure fully open hardware laptop

Project's ambition is to design and deliver an innovative and technically advanced open hardware (RISC-V/ISA) based, European made, inexpensive, FOSS laptop as a personal computing device, containing on board all desirable (FOSS compliant) hardware and software features and functionalities needed to prevent any 3rd party intrusion into the system. It adds physical safety features currently not available in the market such as hot-swappable CPU, hardwired switches for e.g. camera and audio devices, and a quickly removable encrypted hard drive and peripherals. A goal of Balthazar is to enable and educate end users to be private, safe and careful with their own data, and that of others. Another goal is to make computing more sustainable and reach eco-friendly footprint, by empowering users to take up their 'right to repair', through a modular laptop that allows components to be easily exchanged and upgraded - up to the CPU itself. The goal is to lead by example and gently lead other hardware manufacturers to become fully open and transparent. And create an educational platform, as well as an advanced computing device where its users (including those with low income ) to feel secure, safe and comfortable using it. For the children of all ages.

>> Read more about Balthazar - One laptop for the new internet age.

BB3-CM4 — CM4 compatible MCU board

Chip shortages are causing production problems throughout the industry. A way of getting out of the production trap is to get project boards more modular. Popular open hardware projects like the EEZ BB3 T&M (Test & Measurement) device currently depend on specific scarce microcontroller boards, and prospective users face impossible delays and constantly rising prices. This project will relieve some of the tension by delivering special "MCU" boards that are compatible in form factor to widely used MCUs. That way projects gain much more room for fulfilling production needs - allowing them to use alternative pin compatible main modules (like the ULX4M FPGA) without redesign, delivering more flexibility. One additional advantage of this approach is that production of module and base board does not need to be at the same time or by the same company. Hardware upgrades and the right to repair become possible and just involve changing a module, without having to throw out the complete system. Along with the "MCU" module the project delivers a new back plane board for the BB3 T&M device - fully compatible with current design, so existing users can upgrade or replace parts.

>> Read more about BB3-CM4

betrusted — A protected hardware device for your private matters.

Betrusted aims to be a secure communications device that is suitable for everyday use by non-technical users of diverse backgrounds. We believe users shouldn’t have to be experts in supply chain or cryptography to gain access to our ultimate goal: privacy and security one can count on. Today’s “private key only” secure enclave chips are vulnerable to I/O manipulation. This means there is no essential correlation between what a user is told, and what is actually going on. Betrusted will build a full technology stack, including silicon, device, OS, and UX that is open for inspection and verification. Betrusted is a simple, secure, and strong device that aims to advance Internet freedom.

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Betrusted OS — An embedded OS for cryptographic devices

Betrusted OS will underpin the Betrusted ecosystem, and will enable secure process isolation. It will be written a safe systems language - namely Rust - to ensure various components are free from common programming pitfalls and undefined behavior. Unlike modern operating systems that trade security for speed, the Betrusted OS will prioritize security and isolation over performance. For example, it will be a microkernel that utilizes message passing and services rather than a monolithic kernel with modules. Unlike other deeply-embedded operating systems, it will require an MMU, and support multiple threads per process. This will let us add features such as service integrity and signature verification at an application level.

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Betrusted Storage — Plausably deniable encrypted storage

Betrusted aims to be a secure communications device that is suitable for everyday use by non-technical users of diverse backgrounds. We believe users shouldn’t have to be experts in supply chain or cryptography to gain access to our ultimate goal: privacy and security one can count on. Today’s “private key only” secure enclave chips are vulnerable to I/O manipulation. This means there is no essential correlation between what a user is told, and what is actually going on. Betrusted will build a full technology stack, including silicon, device, OS, and UX that is open for inspection and verification. We've passed the first hurdle of creating an FPGA-based device, which we have spun out into a development platform we call Precursor. We are now advancing deeper into the technology stack to improve FPGA, drivers, OS, and UX elements, all driving toward the common goal of making Betrusted a simple, secure, and strong device that aims to advance Internet freedom.

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BrailleRAP — Low-cost open hardware for creating Braille content

BrailleRAP is an open source Braille embosser. AccessBrailleRAP software give you the ability to translate a text document into Braille and emboss the Braille characters on paper with the BrailleRAP device. DesktopBrailleRAP software project aim to build a desktop publishing application suitable to build tactile documents for unsighted people with the Braille embosser BrailleRAP.

The application brings the ability to import vector graphics in SVG format, or create text label with a position and orientation on a page layout. Text labels are translated in Braille with the ability to choose the Braille standard (language in a simplified manner). Vector graphics are decomposed in series of dot positions along path. All dots from Braille characters and paths are converted in GCODE commands for the BrailleRAP embosser. The result is a tactile document with accurate embossed Braille and tactile 2d graphics made by a series of close dots. DesktopBrailleRAP aim to build a suitable tool for individual or teacher to build tactile documents for unsighted people, such as geographic maps, building or organization maps (like school or campus), public transportation maps or teaching plans in biology and mathematics (geometry). The funding from NLnet will allow the development of the first public release with suitable documentation.

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Libre-SOC Cavatools: Power ISA Simulator — Power ISA Simulator

Cavatools is a high performance ISA simulator, similar to qemu. However unlike qemu, cavatools is designed with two goals in mind: to provide accurate guidance on instruction effectiveness, and to run at close to real-time performance on multi-core host systems.

The only hardware that cavatools currently supports is cycle-accurate emulation of RISC-V: this Grant is intended to add not only the Power ISA but also add the Draft SVP64 Cray-style Vector Extensions being developed by Libre-SOC (and sponsored by NLnet). Other work includes being able to verify and compare multiple independent implementations, running the same program, to check interoperability, whether in emulators, hardware simulations, simulators or actual ASICs.

>> Read more about Libre-SOC Cavatools: Power ISA Simulator

LibrEDA — An integrated development environment for chip design

Because digital circuits are a core part of today’s society there is a significant value in free and open chips and, equally important, free and open design software that is accessible also to small entities. Not only would this enhance trust through transparency and digital sovereignty through distributed knowledge but it would also be a fertile ground for education, hobbyists and small enterprises. The main goal of this project is to create a new libre-software framework for the physical design of digital integrated circuits. The framework is meant to simplify the development of chip layout tools, i.e. the tools used to convert a gate-level netlist into a fabrication-ready layout. This includes fundamental data structures and algorithms, interface definitions of the design algorithms (e.g. placement, routing or timing analysis), input/output libraries for commonly used file formats as well as documentation and example implementations. Two variants will be pursued in parallel: One with a clear focus on simplicity and education and another with a focus on performance and scalability. Another part of the project is the continuation of the ‘LibreCell’ standard-cell generator and characterization tool.

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Zerocat Chipflasher Flashrom Interface — Hardware to flash alternative/libre firmware to BIOS chips

The Zerocat Chipflasher Project aims to provide a fully user controlled electronic device, that helps users to remove the proprietary BIOS firmware from their laptops. The tool allows them to instead run verifiable and Free Firmware, produced by the Coreboot and Libreboot project. Proprietary BIOS is opaque with regards to functionality, and may contain known and unknown security issues. Also controversial elements like the Intel Management Engine can be deactivated. The project helps to empower everyone to create trustworthy digital hardware on her or his own and has been successfully certified by the Respects-Your-Freedom (RYF) Certification Program, set up by the Free Software Foundation in Boston, USA. The device combines the Do-it-Yourself concept with free-design hardware development, even down to chip level. This is achieved by skipping convenient functionalities which would require chips of a proprietary design and by instead using a free-design microcontroller, only. The flasher’s integration into the grid of related existing free software projects yet is to be improved by an additional interface and an in depth firmware review.

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Chips4Makers ASICs —

Current scaling of micro-electronics is focused on improving power, performance and cost per device but with an exponentially increasing start-up cost related to the increased process complexity. For the design of custom chips currently expensive proprietary electronic design automation (EDA) tools need to be used and hefty license fees are due for blocks implementing specific functions like the CPU, USB etc. All this together makes custom chip development only accessible for high-volume production and proprietary designs. In this project a development version of the libre licensed Libre-SOC system-on-a-chip will be manufactured in a 0.18um process combined with development on the open source tools and open source chip building blocks to make this possible. Development on the free and open source tools will be focused on making them compatible with the selected process and the building block development will be focused on the so-called standard cell library, the IO library and the SRAM compiler. This project fits in the longer term goal of the Chips4Makers project to make low-volume custom chip production possible using mature process technologies and free and open source tool chains and building blocks. Purpose is to get innovation using custom chips within reach of small start-ups, makers and even hobbyists.

>> Read more about Chips4Makers ASICs

Supersizing the Gun — Chipwhisperer open hardware for side channel analysis

ChipWhisperer is an open hardware and software toolchain that has been a mainstay of hardware security research. ChipWhisperer is used in academic curricula and in industrial R&D implementation security research labs for high speed side-channel power analysis and glitching attacks. The objective of this project is to explore design changes to the current ChipWhisperer hardware, so as to allow capturing of longer power analysis traces and to cater to higher clock speeds than currently supported. Here, the intent is to make it easier to perform side-channel-related analysis of public-key algorithms, without the need to artificially break down the algorithms into multiple components due to platform constraints. This allows for more realistic and practically relevant attacks. This project additionally entails the development of fine-grained post-processing tools, which would make further analysis of captured traces of public-key algorithms easier.

Ultimately, the goal is to work towards candidate post-quantum algorithms, which are known to be more resource-hungry. The project funded by NGI Zero would specifically target design changes to considerably increase the sampling rate (towards 200-250 MS/s) and to provide for a streaming mode (initially envisioned to be roughly 15-30 MS/s). It includes both a new hardware design and a significant update to the current open-source software of the ChipWhisperer platform, as well as demonstration of how to successfully use this with practically relevant ECC public-key algorithms.

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Coloquinte — High performance placement of cells inside digital electronic circuitry

A core component of the ASIC design toolchain is the placement tool, which must decide where to place the components of the chip so that it can be manufactured and meet the performance target. To build chips reliably, improve performance and improve power consumption, the placement tool must interact with other complex tools (routing, timing, gate sizing, ...). This requires a complex integration, and even necessary to target newer technology nodes. Our goal is to provide high-quality placement algorithms with an easy-to-use interface, so it is easy to use in multiple situations and toolchains.

Coloquinte started as a component of the Coriolis toolchain. Since then, it has been made into a library for inclusion in other tools and multiple languages. Current developments target the integration with timing tools (for better chip performance) and routing tools (for power consumption, performance and compilation stability).

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Libre-SOC, Coriolis2 ASIC Layout Collaboration — Open tooling for ASIC Layout

One of the key issues in a trusted, trustable ASIC is for the toolchain to be libre-licensed, so that there is no possibility for hardware-level spying or backdoor compromises. The Alliance / Coriolis2 ASIC layout toolchain by LIP6.fr is one of the leading tools in this area. The Libre-SoC is another project being funded through NGI Zero, and at this moment that project needs to get beyond FPGA-proven status. The challenging next phase is to do an actual ASIC layout. With the System-on-Chip being developed in nmigen (a python-based HDL), Alliance / Coriolis2 also makes sense as it is written in Python as well. The funding will go towards doing an ASIC layout in 180nm.

>> Read more about Libre-SOC, Coriolis2 ASIC Layout Collaboration

DMT — Implementation of MOSFET Parameter Extraction Flow for Sky130 into DMT

DeviceModelingToolkit (DMT) is a Python tool targeted at helping modeling engineers extract model parameters, run circuit and TCAD simulations and automate their infrastructure.

Open PDKs like Skywater130 and IHP SG13G2 have brought about significant disruption in the open-source semiconductor landscape, eliminating barriers and reducing costs for all participants. A reoccurring issue of such open-source PDKs are the compact models. In this project, a compact model parameter extraction flow will be implemented into the open-source device modelling software DMT for generating improved MOSFET compact models for open-source PDKs. These models can be leveraged by circuit designers for cutting edge designs. The parameter extraction tool will be applied to the recently released IHP SG13G2 PDK to demonstrate its usefulness.

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DUT Control — Unified Control Interface for Firmware Security Tests

The DUT Control project aims to create a unified control interface for real hardware used in firmware security tests. Firmware security plays a crucial role on the internet, especially for servers, as it ensures the reliability and trustworthiness of connected devices. However, firmware development poses unique challenges with regard to testing: Firmware runs directly on the hardware and therefore simulations often fail to cover all edge cases, making it essential to test on actual hardware. Furthermore, firmware is tailored to each hardware type, leading to individualized development. Thus, testing often requires manual intervention, increasing time and effort.

DUT Control addresses these challenges by providing an interface to real hardware and an abstraction of hardware inputs and outputs. It is supposed to become the open-source interface between hardware components and testing frameworks.

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Edalize ASIC backend — Create open hardware silicon with a fully free software toolchain

Affordable Open Source ASIC development and custom silicon has been a long-standing goal in the community. This will unlock innovation that has previously only been possible for the largest tech companies, allowing for the creation of deployable, trusted Open Source based hardware.

Step by step, this goal has come closer in the last few years as individuals, companies and academic institutions have filled in the missing pieces. Today we have a fully open source end-to-end flow for building open source ASIC - but the effort of on-boarding existing designs remains high. This project aims to provide an easy way to onboard existing gateware and full designs to an open source ASIC flow by creating a FuseSoC backend that targets this toolchain. This will enable a smoother transition from projects already running on FPGAs to also be targeting ASIC flows. It will also allow easier switching between different open source ASIC flows at the point when there are several alternatives to choose from.

In addition to the backend itself, a reference design containing SERV, the world’s smallest RISC-V CPU, will be run through the flow and committed to actual silicon. This will provide a way to guarantee a working flow and provide a simple but usable reference for everyone else looking to onboard their designs. Enabling and demonstrating this path will allow a fully trustworthy path for the fabrication of system-on-a-chip ICs, with no proprietary or closed tools as part of the flow and hence completely inspectable at all stages. This paves the road for other more complex FuseSoC-based open source silicon projects such as OpenTitan and SweRVolf.

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EEZ DIB — EEZ DIY Instrument Bus

The aim of the EEZ DIB project is to enable the creating and management of modular open hardware T&M (Test & Measurement) solutions. Born out of frustration that solutions from reputable manufacturers are feature rich but closed in design and with expensive software licenses, an attempt have been made to fill the gap between such solutions and DIY/hobbyists solutions which although often open in design lack structure, documentation and completeness that could ensure further growth, development and support.

The hardware part of the project is EEZ BB3, an open source DIB chassis in a compact format that can accommodate up to 3 peripheral T&M modules which can be monitored locally via touchscreen display with responsive and attractive user interface or remotely via USB or Ethernet using Telnet, MQTT, JS and Node-RED. Additional autonomy and programmability has been achieved by adding support for MicroPython scripting.

The software part of the project is EEZ Studio, a free and open source cross-platform application that has two functions: a) visual editor that simplify and accelerate touchscreen GUI development and b) management of multiple EEZ BB3 and 3rd party T&M devices for the purpose of simple communication and acquisition, search and presentation of measurement data.

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EDeA — A forge suitable for open hardware development

The short version: EDeA is a novel approach to allow exploration of and improve discovery within the open hardware ecosystem - in order to help make open hardware designs and components discoverable and reusable.

At this moment in time, pretty much everything surrounding open hardware development is manual. Beyond just typing something into a generic search engine there isn't really suitable tooling available to search across what already exists. Accessible and usable distributions, collaboration tools and version control are what drove the free and open source software revolution, now open hardware needs to take the same leap forward.

Open hardware electronics projects are growing in numbers, thanks to crowdfunding, a strong developer community, and sophisticated open source electronic design automation (EDA) tools like KiCad. Between circuit schematic and printed circuit board (PCB) layout there is a logical association, but are being handled by separate programs, and therefore one can’t simply copy-paste design blocks. In 2020 it is still next to impossible to reuse proven parts of different designs without needless reimplementation. By leveraging KiCad’s pcbnew and eeschema scripting, a new way of building modular, reusable electronics opens. We are creating a catalog and community portal for discovery and development of proven circuit modules: power management, signal conditioning, data conversion, micro-controllers, etc.

>> Read more about EDeA

f8 — Modern 8-bit instruction set

Among microcontrollers (µC), 8/16-bit µC are an important part of the embedded systems ecosystem since they tend to have substantially lower resource and energy costs than the larger, more powerful 32-bit and 64-bit µC.

However, existing 8/16-bit µC architectures tend to be either somewhat inefficient (e.g. MCS-51) or single-vendor (e.g. STM8, Rabbit). The latter are at a high risk of being discontinued when a vendor pulls out of the 8/16-bit market, and this has been announced recently for the STM8 and Rabbit architectures. One possible solution is to develop an efficient free architecture for 8/16-bit µC. The f8 is such an approach. It is based upon extensive experience from the large number of 8/16-bit architectures supported by the free Small Device C compiler (SDCC). Like RISC-V did for 32/64-bit architectures, f8 is based on lessons learned from the strengths and weaknesses of existing 8/16-bit architectures.

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FABulous Demo SoC — SoC with open source FPGA based on FABulous

Until recently, integrated circuits have largely been treated as blackboxes in the realm of trustworthy hardware. FPGAs, devices that can be programmed by the user to implement arbitrary logic functionality, help to open up this realm. But even with open source software stacks such as Yosys and nextpnr compiling for them, FPGAs themselves are still proprietary silicon. Using the FABulous framework and a wide range of other open IP, we are building a FPGA SoC (combination of a FPGA programmable logic fabric and a Linux-capable RISC-V CPU) that is both itself open source and built with open tools, and also supports the open FPGA toolchain. to develop it. Simplicity is a key design decision throughout, so we can use our work to explain how modern computing systems work without the complexity of commercial platforms.

>> Read more about FABulous Demo SoC

FastWave — Modern waveform VCD parser

Whilst the fields of open-source hardware design tooling (including synthesizers and layout tools, and open-source digital logic/VLSI gateware) have recently experienced a significant renaissance, simulation visualization tools have not enjoyed similar advancements. This is noteworthy given that verification comprises approximately 80% of the digital logic development cycle. Efficient visualization and debugging of SOC simulations are thus becoming ever more critical.

Fastwave, currently developed as a VCD (Value Change Dump) parser in Rust, along with its visualization frontend, Surfer, aims to address this gap. Future iterations of Fastwave will enable advanced visualization of simulation states through custom user plugins. Potential applications include, but are not limited to, visualizing CPU pipeline states with pipeline diagrams or representing mesh network activity by simply loading a VCD file. Plans for expanding the Fastwave suite include features like tracing signals to their source, allowing users to pinpoint the HDL conditions that prompted changes in simulation signal states. Ultimately, Fastwave intends to reduce the workload for digital logic designers by enabling them to align the tool's visual outputs with the mental models they already have of their hardware systems.

>> Read more about FastWave

FemtoStar Project — Open Hardware Communications Satellite

The FemtoStar Project is developing a low-cost communications satellite, intended for use as part of a scalable, decentralized network enabling verifiably anonymous, geolocation-resistant communications on a global scale. While many anonymizer services are currently available to users of existing communications systems, these serve simply to separate knowledge of identity (which still lies with the communications service provider) from knowledge of activity (which lies at the exit of the anonymizer service). All current wide-area communications networks are fundamentally identifying (users and their hardware are, at minimum, pseudonymous to the network) and no two-way communications system offers any meaningful degree of resistance to geolocation of the user. The FemtoStar Project intends to use a constellation of FemtoStar satellites to provide global, space-based open communications infrastructure linking users to services (which can be operated by anyone, and require no special ground station installation beyond a regular FemtoStar user terminal) or directly to other users, and requiring no identification or geolocation of user terminals. We are seeking funding for the development of a prototype satellite and user terminal, implementation and testing of the FemtoStar protocol on this hardware, and, dependent on funding amount and regulatory approval, the licensing and launch of one FemtoStar satellite to low earth orbit for system testing and, possibly, for use in a limited open beta service. With prototype hardware and, ideally, with one production satellite in orbit, the FemtoStar Project will be able to validate the FemtoStar system and move towards our goal of operating a scalable constellation for global, verifiably-private communications service - a world-first in privacy technology.

>> Read more about FemtoStar Project

Flashkeeper — Write Protection on SOIC-8 flash chips without soldering

Firmware security projects such as Heads assume the firmware itself to be protected against tampering. Outside of proprietary solutions Boot Guard, partial write protection (WP) of the SPI flash chip (recently implemented by 3mdeb) is one solution. However, WP requires grounding the chip's WP pin, something that currently requires users to solder to the chip. As many users find this difficult, this has limited "retrofit" adoption of WP.

This project is developing Flashkeeper, a device that can be permanently installed on a common SOIC-8 flash chip. It attaches to the chip with a peel-and-stick layer and spring-loaded contacts or low-profile solder-down flex cable, interfacing with the SPI flash pins for easy write protection and external reprogramming (unbricking). For users concerned with physical attacks on their systems, for whom easy access to SPI flash pins may be seen as a risk, a variant including a microcontroller (MCU) is also being developed, allowing authenticated external reprogramming and WP control, and independently verifying the SPI flash image against a user-controlled signature each boot.

>> Read more about Flashkeeper

foaHandler — Reverse engineer the OpenAccess file format

Commercial CAE programs still dominate the community that designs electronic circuits. One of the most widely used file format here uses the OpenAccess API controlled by Si2. Unfortunately, this API is available only for members of the OpenAccess coalition. The project "foaHandler" aims at creating open-source programs for reading and writing OpenAccess files. Their internal data structure will be investigated by reverse engineering the file content of schematics, component symbols and layouts. Then, routines will be created that make it easy to import and export OpenAccess files in open-source programs like circuit simulators, layout programs etc. Example files and documentation will be published, too. This makes the data exchange between free and commercial EDA applications possible.

>> Read more about foaHandler

Fobnail — Remote attestation delivered locally

The Fobnail Token is a tiny open-source hardware USB device that provides a means for a user/administrator/enterprise to determine the integrity of a system. To make this determination, Fobnail functions as an attestor capable of validating attestation assertions made by the system. As an independent device, Fobnail provides a high degree of assurance that an infected system cannot influence Fobnail as it inspects the attestations made by the system. Fobnail software is an open-source implementation of the iTurtle security architecture concept presented at HotSec07; in addition, it will leverage industry standards like TCG D-RTM trusted execution environment and IEFT RATS. The Fobnail project aims to provide a reference architecture for building offline integrity measurement servers on the USB device and clients running in Dynamically Launched Measured Environments (DLME). It allows the Fobnail owner to verify the trustworthiness of the running system before performing any sensitive operation. Fobnail does not need an Internet connection what makes it immune to the network stack and remote infrastructure attacks. It brings the power of solid system integrity validation to the individual in a privacy-preserving solution.

>> Read more about Fobnail

FPGA Fault Injection Testing — Better testing towards preventing fault injection in FPGA's

Fault injection aims at disrupting the orderly way in which data and instructions in a chip are processed. This can be achieved, e.g., by malicious glitches that briefly interrupt the supplied voltage of the chip. To better protect against faults, countermeasures need to be implemented, such as glitch sensors that can detect these adversarial conditions. Due to the wide range of fault injection methods, the development of glitch sensors is time-consuming and requires a wide range of lab capabilities.

Within the context of FPGAs, such testing is often not feasible due to their unique configuration based on a bitstream. In this project we seek to demonstrate that in-situ fault injection by creating short-circuits in an FPGA is possible and that this can be used to emulate similar effects in the circuit that otherwise would require costly external instruments. In addition, since FPGAs can be reconfigured quickly, it is possible to rapidly test a wide range of fault injection configurations. We then implement and compare glitch sensor designs in the FPGA and compare them to the state of the art (attacks and countermeasures) with the expectation to improve over previous results, as the fine-grained in-situ fault injection process is expected to offer more control over the testing process, resulting in a better calibration of the glitch sensor.

>> Read more about FPGA Fault Injection Testing

FPGA-ISP-UVC-USB2 — Open hardware FPGA-based USB webcam

The USB UVC project is designed to create an innovative and adaptable webcam that easily connects to any laptop, providing high-quality video without the need for special drivers. Unlike ordinary USB webcams that often come with proprietary software and limited functionality, this project aims to deliver a flexible, open-source solution that can be tailored and improved by anyone. The webcam will offer superior video quality with features like automatic brightness adjustment, color correction, and real-time video compression, making it ideal for video calls, streaming, and other visual applications. By focusing on open-source principles, this project ensures that the technology is accessible, modifiable, and transparent, allowing for continuous community-driven enhancements.

This project stands out because it is not locked into proprietary ecosystems, offering users greater control and flexibility over their hardware. It can work with a wide range of computer models, providing a versatile tool for both personal and professional use. Additionally, the open-source nature of the project means that it can be continuously improved and customized by developers around the world, fostering innovation and collaboration.

>> Read more about FPGA-ISP-UVC-USB2

Frugal EDA — Energy-efficient circuits and systems through quantum superconductivity

FRUGAL EDA is an open-source user-friendly software design suite dedicated to energy-frugal electronics based on the amazing quantum physical properties of superconductivity. Its objective is to enable the design of energy-efficient ultra-high-speed (up to clock frequencies of several hundreds GHz) quantum-based circuits and systems for the widest possible audience. FRUGAL will emulate the development of new circuits and functionalities so that disruptive quantum electronics can take its place in the current highly-competitive emerging technology landscape. One goal is to increase the number of students and newcomers interested to design quantum-based circuits without the need of unaffordable tools, proprietary technologies or steep learning curves.FRUGAL embeds a set of open-source software tools comprising a schematic editor(LibrePCB), a SPICE netlist converter (L2SPICE), quantum time-domain simulators (JSIM and JoSIM) and a layout editor (KLayout). More designer-oriented features will be added along the course of development.

>> Read more about Frugal EDA

Libre/OpenCores FuseSoc backend — Discovery and use of open hardware gateware through LibreCores and OpenCores

Chip (FPGA/ASIC) development is normally done in a very hierarchical manner where gateware is used to build up subsystems which are combined to a full chip design. On paper, this leans very well for reusing parts in many different chip designs, but the actual amount of reuse has always been hampered by the lack of tooling to manage and combine gateware. Compare this to the software world where languages such as JavaScript, Python or Rust have a rich ecosystem of user-created reusable parts that can be used as a base to quickly build new applications. This project aims to provide a similar ecosystem for chip development where users can publish their cores, find the cores they need and build upon these to rapidly create new designs.

>> Read more about Libre/OpenCores FuseSoc backend

Collection of Verified multi-platform Gatewares — Comprehensive repository of open source gateware designs

The "Verified Multi-Platform Gatewares" project will create a comprehensive repository of gateware designs that are compatible with various FPGA development environments and boards. The goal is to reduce the barriers to FPGA development by providing designs that are rigorously tested and maintained for compatibility. The project will host these open source designs on a dedicated website, ensuring they work seamlessly across multiple toolchains and boards. The collection will range from beginner to advanced designs, serving as educational resources and benchmarking tools, continually updated to prevent bitrot.

>> Read more about Collection of Verified multi-platform Gatewares

Verilog-AMS in Gnucap (cont'd) — Analog/Mixed modelling and simulation in Gnucap

Verilog-AMS is a standardised modelling language widely used in analog and mixed-signal design, but without an open reference implementation. Gnucap is a modular mixed-signal circuit simulator that partially implements Verilog-AMS, that aspires to eventually implement the complete language. In 2023, with NLnet support, we made significant progress in support for Verilog-AMS, the "analog" part, also known as Verilog-A, both on the simulator side and in the model compiler. For 2024, we will extend the work, concentrating on three tasks. The first is extensions to modelgen, the model compiler, essentially completing the analog part of Verilog-AMS, with some digital. The second task is enhancements to the simulator, mostly related to fast simulation of large mixed circuits, with both analog and digital parts. The first and second tasks are related to the "mixed-signal" aspect of Verilog-AMS. The third task addresses interoperability with other software, including schematic entry and layout, ability for Gnucap to use device models from other simulators, for modelgen to generate code to be used with other simulators, and porting some analysis commands.

>> Read more about Verilog-AMS in Gnucap (cont'd)

Verilog-AMS in Gnucap — Mixed-signal modelling and simulation with Verilog-AMS

Verilog-AMS is a standardised modelling language widely used in analog and mixed-signal design, but without an open reference implementation. The language supports high-level behavioural descriptions as well as structural descriptions of systems and components. This Project will make substantial progress towards a Gnucap based free/libre Verilog-AMS implementation. Gnucap is a modular mixed-signal circuit simulator, and has been released under a copyleft license with the intent to avoid patent issues. Gnucap provides partial support for structural Verilog and encompasses an analog modelling language that has influenced the Verilog standards. We will enhance data structures and algorithms in Gnucap, and improve Verilog support on the simulator level. We will implement a Verilog-AMS behavioural model generator targetting Gnucap with the intent to support simulators with similar architecture later on.

>> Read more about Verilog-AMS in Gnucap

Porting Guix to Riscv64 — Port Guix software collection to Riscv64 architecture

This project will work on bringing the Rust support of GNU Guix on Riscv64 up to fully supported, with the bootstrap chain from source. It will also bring Riscv64 in Guix up to the full level of support that is expected of commonly used architectures, ready to be used in all the applications where GNU Guix is already found. Riscv64, being an Open Architecture, freely available to anyone who wants to implement processors, goes a long way towards ensuring that our future computing platforms are free of hidden backdoors. GNU Guix, being a true Free Software Operating System and compiled from source from a small bootstrap binary, with reproducibility guarantees, is as close as the computing community has come to a fully auditable software chain that makes sure all the software we run on our computers is what we intend, and nothing more. By combining the Riscv64 architecture and GNU Guix for software we can reach toward a fully secure and auditable computing platform that we might consider trusting.

>> Read more about Porting Guix to Riscv64

Hardware accelerated 2D graphics — Design hardware accelerated 2D graphics using C to Verilog

This project is to develop a hardware accelerated 2D video controller for easily adding user interfaces to industrial and commercial machines. Besides offering a useful product and fulfilling a long-standing need for embedded systems development, it will also encourage people to engage in FPGA-based hardware development by using more friendly tools.Traditionally, to make stand-alone machines and systems (i.e. not based on PCs but on custom computing boards), if developers need to add graphical user interfaces (GUI) they are offered only two inconvenient options: use a complex system like a Linux-capable board, or limit performance to low resolutions that are unsuitable for medium to large displays. The latter case simply prevents successfully marketing those products, while the former requires a high degree of qualifications in embedded systems development, to build simple products like signage systems or vending machines. This project is somewhat inspired by the success of the Arduino project, a product and ecosystem that greatly simplified the design of not too complex machines, and encouraged a lot of people to do their own designs. Currently, with the easier Arduino and similar systems, there's no way to control professional user interfaces, so many developers keep outside of the field. With the proposed system, instead, it is easy: you can send drawing commands to the board right from the Arduino system, through a provided library. The board then loads previously stored images and fonts to render the GUI at a high resolution. The drawing commands are implemented with hardware acceleration to meet speed needs, and the cores for achieving that (FPGA gateware) will be written in the widely known C language. This is solved with a custom tool for conversion to Verilog, that offers fast graphical simulations too. This will encourage people who know the language from software development, to enter the hardware design field. Also, the widely known and easy to learn Micropython language will be offered, to further ease implementing devices.

>> Read more about Hardware accelerated 2D graphics

Open Hardware Manuals — Automatically generate user-friendly documentation for open hardware elements

This project will create a tool that automatically generates Computer-Aided Design (CAD) models, assembly documentation, graphics, and user guides based on user provided configurations. These documents can be continuously updated, localized, and are shareable - akin to an always up-to-date Ikea-style assembly guide. The tools developed during this project will also be applicable to other open hardware projects, empowering designers to produce hardware that is more adapted to specific contexts, without creating fragile documentation that always goes out of date when a change is made to the design.

>> Read more about Open Hardware Manuals

Icestudio — Visual developer tool for development of FPGAs

Icestudio is an open source integrated development environment (IDE) with a "no code" philosophy that, through a block and diagram oriented visual interface, simplifies and streamlines the design of digital electronics on FPGAs. The simplicity of the concept breaks with the complexity of other tools in proprietary EDA environments, being able to meet the educational needs of STEM disciplines for the youngest students in schools, institutes, and universities, as well as providing more advanced users with a tool that simplifies their workflow in a much more user-friendly and visual environment without losing power or control.

Through its frictionless installation system and the generation of Verilog code from the visual design, Icestudio allows users to get started immediately, acting as an integrating element between designers and manufacturers of open hardware, with developers of open software solutions for synthesis such as Oss Cad Suite and transpilers such as Silice, Amaranth, or Cflexhdl.

Icestudio has the vocation of becoming the standard as a visual IDE for digital design on FPGAs, allowing other code-oriented IDEs to integrate it as part of their solution in the near future.

>> Read more about Icestudio

IC workspace — Open Source IC Design Management Tool

IC workspace is a design management tool that addresses the complexity of working with scattered design domains that span analog, digital, EDA tools, flows and process development kits (PDKs). In the process of designing a chip, multiple people need an common organized structure to work on design capturing schematics, generator, custom layout, high level digital design combined with test benches in various domain specific formats. Each tool in the open source domain has it own file structure. IC workspace is an open source framework with tools that individual designers and teams use to organize design files in a local workspace. IC workspace integrates interface to source code version control systems, the various tools in the design flow and organizes the files in a workspace with an unified component structure with dependency attributes. IC workspace sets common language and methodologies for both analog and digital – frontend/backend designer to maximize productivity within the open source chip design ecosystem of tools, PDK’s and people.

>> Read more about IC workspace

YunoHost and the Internet Cube — Solutions for DIY-ISP's and self-hosters

YunoHost is a free and open-source server distribution that provides a self-hosted alternative to commercial centralized services, and allows people to take back control over their data. Yunohost aims to make server administration accessible to the general public and ultimately make personal servers as common as desktop computers. Based on YunoHost, the Internet Cube project develops an affordable plug-and-play server that can be bought and easily deployed at home by the general public. In addition to its self-hosting capabilities, it provides a privacy-enhancing WiFi hotspot which protects its users from censorship and metadata leaks. And because it is low-power, it can be used even in remote and offline situations.

>> Read more about YunoHost and the Internet Cube

JellyfishOPP — Open Hardware device for power profiling

JellyfishOPP (Open Power Profiler) is an affordable open-hardware measurement device designed to provide advanced, bidirectional power measurements and profiling, power optimizations, and battery profiling/simulation. It primarily targets developers of ultra-low power devices such as IoT sensors and wearable electronics, while also serving engineers and hobbyists. OPP will be a portable USB device that can be controlled through a host computer or smartphone app. Additionally, it will feature a simple on-device user interface for basic functionalities, eliminating the need for a host device in certain scenarios.

>> Read more about JellyfishOPP

KiCad-IPC — Add RPC API, multichannel designs and schematic variant system to FOSS EDA suite

KiCad is an open source electronics design application (EDA) suite. The program includes schematic capture, printed circuit board (PCB) layout, circuit simulation, 3D viewer, and many other tools to provide the best possible user experience for professional electronics designers while still remaining approachable for new and inexperienced users. It is available for Windows, macOS, and Linux and is released under the GPL3+ license.

>> Read more about KiCad-IPC

KiKit — Tooling for automation of production of PCB designed in KiCAD

The EDA suite KiCAD is a widespread libre solution for designing electronics. KiKit is a Python library, KiCAD plugin, and a CLI tool to automate several tasks in a standard KiCAD workflow. The main goal of KiKit is to make the step from finishing a PCB design to having a physical PCB as easy as possible, as fast as possible, and as error-proof as possible. It achieves that via automation of manufacturing data preparation. The automated processes are reliable, repeatable, and require zero designer input. Thus, they are error-proof. KiKit allows you to perform sanity checks of the PCBs, build panels according to the description and generate manufacturing data (gerbers, assembly files, BOMs, stencils), PCB documentation, and more. All this can be fully automated and, e.g., integrated into continuous-integration pipelines. Not only KiKit provides ready-to-use pipelines for the most common scenarios, but it can also serve as a framework for building custom PCB post-processing setups.

>> Read more about KiKit

Kintex-nextpnr — Open toolchain for high performance FPGAs

FPGAs are reconfigurable chips capable of handling many electronic signals in parallel. They are used in network equipment like backbone switches, firewalls, video devices like surveillance cameras and radio equipment like mobile-phone base stations and radar systems and satellites to process high volumes of data with very low latency. FPGAs are also used to test digital circuit designs before they are manufactured as chips.

The functionality of FPGAs is determined by a configuration file which is loaded into the FPGA at power-on. The configuration file is usually generated from a design file by a proprietary closed source tool provided by the manufacturer of the FPGA. nextpnr-Kintex will provide a complete set of open source tools to generate a configuration file for the widely used family of Kintex7 FPGAs from manufacturer Xilinx/AMD without having to use any proprietary tools. This will empower digital design engineers to have the guarantee that no backdoor is implemented on FPGA based devices by the proprietary design tool provided by the vendor. The availability of the source code of the FPGA design tool will also allow innovators to come up with new use cases for FPGAs currently not possible with proprietary tools. Overall, the project will help to increase the security of FPGA based wired and wireless network infrastructure in Europe.

>> Read more about Kintex-nextpnr

Wireguard-1GE FPGA — Implement Wireguard in Verilog

WireGuard is a modern data tunneling and encryption protocol for Internet security. Traditional VPN solutions such as OpenVPN and IPSec are outdated, bloated, and have security gaps. While WireGuard in many cases will be a superior alternative, the performance of a software implementation will not always be enough for high-throughput use cases.

The project will implement the WireGuard protocol on a cost-effective Artix-7 FPGA, targeting a board supported by open-source tools for Xilinx with four 1Gbps Ethernet ports. The corresponding gateware will be written in the industry-standard Verilog, welcoming everyone to contribute and review our code, helping us make it more secure and widely used.

This project promises to deliver a working prototype of WireGuard in hardware in complete alignment with the spirit of the open-source movement.

>> Read more about Wireguard-1GE FPGA

Langsec in Pectore — A secure pacemaker created from formal grammars

Design and build a Proof-of-Concept (PoC) cardiac pacemaker circuit with an analog/mixed-signal CMOS ASIC based on a description of the device functionality as formal grammar/automaton based on language security (langsec) design principles. Internet-of-things (IoT) devices are usually designed around a general purpose microcontroller with a much larger state space than needed for their purpose. Only after the initial design, interface capabilities of the IoT device are artificially restricted for privacy and security. An implanted pacemaker is a safety-critical IoT device that fits into a very small state space, as proven by early pacemaker designs that did not use high performance microcontrollers. Langsec methods use formal grammars to specify minimal interface parsers to reduce the attack surface, but not the attack volume behind the attack surface. As PoC, formal langsec methods are adapted to reduce the attack volume of a pacemaker: A domain-specific language (DSL) translates requirements of a cardiac pacemaker patient and an information security researcher (ideally one and the same person) into an implantable minimum state space analog/mixed signal pacemaker application specific integrated circuit (ASIC). Such a minimum automaton methodology can be transfered to less life-critical IoT devices. ASICs for minimum automaton IoT designs are a use case for completely free CMOS IC fabrication processes, e.g., LibreSilicon. Non-essential state space that isn't implemented can't be hacked.

>> Read more about Langsec in Pectore

LibreCellular — FOSS technology stack for 4G networks

The LibreCellular project makes it easier to create 4G cellular networks with open source software and low cost software-defined radio (SDR) hardware. Achieving this via validated hardware and software configurations that are subjected to rigorous end-to-end testing via a continuous integration (CI) platform, supported by tooling and documentation for repeatable deployment.

This NLnet funded work will build on previous efforts and enable the integration of a more advanced core network, together with support for Voice-over-LTE (VoLTE). In support of which the existing CI hardware platform will also be extended and tests developed to provide VoLTE coverage. Finally, a previously developed medium power RF amplifier will be further developed to create a complete RF front-end, and a deployment manual will be created which covers topics such as antenna selection, spectrum licensing and EMF assessments.

>> Read more about LibreCellular

LibrePCB — EDA software suite to develop printed circuit boards

LibrePCB is a free and open source electronics design automation (EDA) software suite to develop printed circuit boards (PCBs). It runs on all major platforms and aims to be easy to use, while still beeing able to create professional schematics and PCBs. The goal is to make creating electronics easier, more efficient and less error-prone by using modern technologies and user interface concepts. LibrePCB therefore streamlines the whole PCB design process — from installing part libraries to ordering the final PCB design. Having such a free, powerful EDA software is the basement for the whole open hardware community as it allows us to reduce the dependency to proprietary and expensive technologies and empowers everyone to develop hardware for free, from hobbyists to professionals.

>> Read more about LibrePCB

LibrePCB 2.0 — New UI & powerful features for a future-proof LibrePCB

LibrePCB is a free and open source electronics design automation (EDA) software suite to develop printed circuit boards (PCBs). It runs on all major platforms and aims to be easy to use, while still beeing able to create professional schematics and PCBs. While it is already used productively by people all around the world, the development of new features became to stuck because of limitations of the current UI concept. To pave the way for new features, a completely new UI will be developed with the goal of having a unified, tabbed window as known and proven by many other applications. In addition, a first attempt of moving from C++ to the safer language Rust will help us to benefit from modern technologies. Together with more import/export capabilities, performance improvements and other frequently requested features the outcome will be released to users by a new major version LibrePCB 2.0.

>> Read more about LibrePCB 2.0

Libre-SOC — A fully open hardware System-on-a-Chip

It is 2019 and it is not possible to buy a mass-produced laptop, tablet or smartphone and replace all of its software (with software that a user can trust) without loss of functionality. Processor boot-loaders are DRM-locked; WIFI, 3D Graphics and Video Processors are proprietary, and Intel's processors contain problematic features and intransparent elements such as the "Management" Engine. The most logical way to restore and engender trust is to literally make a new processor - one that is developed transparently and may be independently audited to the bedrock. The project develops a low-power, mobile-class, 64-bit Quad-Core OpenPower SoC at a minimum 800mhz clock rate, suitable for tablet, netbook, and industrial embedded systems. Full source code files are available for the operating system and bootloader, and the actual processor, its peripherals and its 3D GPU and VPU. Details at https://libre-soc.org/3d_gpu/

>> Read more about Libre-SOC

LibreSilicon — Free/open source semiconductor manufacturing process

LibreSilicon aims to reduce the steep entry barriers to full custom application-specific integrated circuit (ASIC) design and help people to regain trust in their computing devices, right at the bedrock: When they are manufactured. LibreSilicon provides a standard for manufacturing semiconductors which allows platform independent process design kits (PDKs) and design rules that allow manufacturing the same chip layout in any factory that has calibrated their process according to the LibreSilicon specs. By introducing this process standard, full custom ASIC design should become available to private persons without corporate or academic access to IC foundries. After democratizing software development with tools like Arduino, and PCB design with tools like KiCAD, LibreSilicon will democratize ASIC design, and GDS2 intends to become the new Gerber file format for semiconductor manufacturing.

>> Read more about LibreSilicon

Libre Silicon compiler — Synthesize, place and route hardware description to silicon

LibreSilicon Compiler (LSC) is a place + route suite for silicon. The main focus of this project is to produce legal and efficient silicon layouts from digital netlists (e. g. BLIF, EDIF). Traditionally the placement and routing problem are handled separately and in sequence and the final layout is given by the routing step. In this setup the routing step gains information from placement but not the other way around. LSC attempts to shift this paradigm to create a feedback loop between the two main problems to improve the solution. Furthermore we are incorporating formal methods to produce the compiler software and to verify resulting layouts. While the latter is standard practice, proving properties of the compiler software itself is only widespread in the domain of software compilers. This exercise will be favored by the use of the programming language Haskell and advanced theorem provers. Finally this software aims to profit from explicit module hierarchies given by the developers of digital logic in register-transfer level (e. g. Verilog, Chisel). Greedy solutions can be found for highly modularised chips: when logic is not inlined in the conventional software compiler sense, the size of problem instances is kept small. This also gives parallelism for free, as the dependency tree is resolved from the bottom up.

>> Read more about Libre Silicon compiler

Standard Cell Library — Open Standard Cell Library with automated dimensioning of transistors

Without having an open standard cell library, any open hardware project depends on unknown components. This significantly hampers innovation, and is on the critical path of delivering truly open hardware chips. LibreSilicon's approach to this problem is generative, working from a (potentially verifiable) algorithm for automated sizing of transistors. All commercial available Standard Cell Libraries contain a small subset of all useful cells only, limited by the manpower of the vendor. They are hand-crafted and error-prone, and typically require Non-disclosure agreement (NDAs) while heavily depending on the underlaying PDKs - meaning that the outcome is hard to verify and trust. Goal it so produce a production quality free and open source Standard Cell Library.

>> Read more about Standard Cell Library

Port of AMDVLK/RADV 3D Driver to the Libre-SOC — Adapt Vulkan Drivers to the Libre-SoC

The Libre SoC is being developed to provide a privacy-respecting modern processor, developed transparently and as libre to the bedrock as possible. As a hybrid processor, it is intended to be both a CPU and a GPU. GPUs are typically proprietary (and thus not fully transparent), as is the 3D driver software. The SoC design requires a Vulkan compliant hybrid hardware-software API. The development of the Kazan 3D Driver (developed from scratch inside the Libre SoC) that aims to provide such an API is therefore on the critical path to final release. Given the complex nature of 3D driver development, and because Kazan is a novel approach (written in rust, for security reasons) that dependency is considered a liability. This project develops a second, more traditional Mesa3D driver in c++. This reduces the pressure on the Kazan development, and allows for benchmarking and increased transparency and collaboration on this ambitious project.

>> Read more about Port of AMDVLK/RADV 3D Driver to the Libre-SOC

The Libre-SOC Gigabit Router — Native Open Hardware chip implementation of crypto primitives

The Libre-SOC Project is developing a Libre System-on-a-Chip in a transparent fashion to engender end-user trust. Based on the OpenPOWER ISA, the next logical step is to extend and modernise OpenPOWER into the cryptographic and blockchain realm, and to do so in a practical way: design a Router ASIC. Whilst many commercial ASICs would do this using hard-coded non-transparent blocks or instructions, true transparency really only exists if the ISA has general-purpose primitives that can be Formally (mathematically) validated. The Libre-SOC Crypto-router Project therefore goes back to mathematical "first principles" to provide general-purpose Galois-Field, Matrix abstraction and more, on top of Simple-V Vectorisation. This provides flexibility for future cryptographic and blockchain algorithms on a firm transparent foundation.

>> Read more about The Libre-SOC Gigabit Router

Libre-SOC HPC — Work on High Performance Compute capabilities for Libre-SOC

LibreSOC has made significant progress in the development of Digitally-Sovereign VLSI designs. This project will continue to further that initial research to create High Performance Compute capabilities for ultimate use in end-user products such as smartphones, desktops, laptops and Industrial Embedded PCs is clearly important. We therefore aim to further the IEEE754 Pipelines, associated Formal Correctness Proofs, and continue implementing unit tests, Simulator, Processor Core implementing Power ISA and Draft SVP64, as well as documentation. In order to engage with developers and solicit feedback we wlll present the progress and outcomes at relevant technical conferences.

>> Read more about Libre-SOC HPC

Libre-SOC OpenPOWER ISA WG — Steward ISA extension proposals through OpenPOWER External RFC Process

The Libre-SOC project has developed Draft SVP64 (a Vector Extension for the Power ISA), containing around a hundred new Draft instructions that dramatically improves the Supercomputing-class Power ISA. It also produced a Simulator, thousands of unit tests and over 350 pages of documentation. What we could not do however was submit a Specification to the OpenPOWER ISA Working Group - because the ISA WG was still in the process of being ratified. That has now been done, and we need to begin the formal process of writing up "Requests For Change" and submitting them. The end result will be an extremely powerful Vector ISA suitable for use in Digitally-Sovereign end-user products.

>> Read more about Libre-SOC OpenPOWER ISA WG

Libre-SOC Formal Correctness Proofs — Mathematical unit tests for open hardware System-on-Chip

Hardware projects like the Libre-SOC Project involve writing an inordinate amount of comprehensive unit tests to make sure everything functions the way it should. This is a critical and expensive part of the overall design process. Formal Mathematical Proofs (already quite popular in secure software development) provide an interesting alternative for several reasons: they're mathematically inviolate, which we believe makes them more trustworthy. And they are simpler to read and much more comprehensive (100% coverage), saving hugely on development and maintenance. From a security and trust perspective, both aspects are extremely important. Security mistakes are often accidental due to complexity: a reduction in complexity helps avoid mistakes. Secondly: independent auditing of the processor is a matter of running the formal proofs. The project aims to provide proofs for every module of the Libre RISC-V SoC, and therefore contributes significantly with the larger goal of developing a privacy-respecting processor in a way that is independently verifiable.

>> Read more about Libre-SOC Formal Correctness Proofs

Libre-SOC Formal Standards Development — Formal Standards for OpenPower extensions from Libre-SoC

Libre-SOC was first funded from NLnet in 2018. This was for the core of the project, based on an informally-developed Hybrid CPU-GPU 3D instruction set that had been written (and implemented in a simulator) in the 18 months prior to contacting NLnet. During the implementation it became clear that a lot more work is needed, and, further, that to meet proper transparency criteria, the proposed instruction set enhancements would need to be properly written up. In addition, negotiations and communications with the Standards Body responsible for POWER ISA (the OpenPower Foundation) also needed to be taken into consideration. The goal of this project is to deliver on those requirements, and achieve full transparency and understanding of the Libre-SoC.

>> Read more about Libre-SOC Formal Standards Development

Libre-SOC Video Acceleration — Optimised video acceleration instructions for Libre RISC-V SoC

The Libre-SoC Project, has been funded by NLnet to get to FPGA-proven status. This was for the "core" (the main processor). One of the next, specialist, phases, is to ensure that its capabilities are useable to perform Video Acceleration. To do so, Video Software such as ffmpeg, gstreamer and their low-level libraries need to actually use the hardware-accelerated capability. A "normal" commercial processor usually has a separate proprietary VPU, along with proprietary software: both unfortunately are vectors for attack against users, undermining trust and privacy. Without access to Video Acceleration, users are left with the stark choice: be compromised, or don't watch any video, period. This project therefore provides a commercial-grade Video Decoder (minimum 720p) and helps restore trust in the software *and* hardware.

>> Read more about Libre-SOC Video Acceleration

LiteX — Developer framework for FPGA and ASIC designs

LiteX is a versatile Python-based framework designed for building FPGA SoCs, providing a useful tool for developers working with FPGA and ASIC designs. Within this project we will improve LiteX by simplifying its use across three main tasks: creating FPGA-based accelerators and innovative ASIC SoCs, and running CI tests on FPGA boards.

For supporting FPGA-based accelerators we will develop a user-friendly infrastructure for developers to create their own accelerators using their preferred HDL language, along with example projects and documentation for various FPGA boards. We will extend LiteX CI tests to hardware to maintain stability, avoid regressions when introducing new features and enable testing of configurations that are difficult or impossible to simulate. And by introduce ASIC support to LiteX we enable people to create innovative ASIC SoCs. We start with a SKY130 build backend, and will extend the framework to streamline switching between different flows: Simulation, FPGA prototyping, and ASIC. We subsequently collaborate with other NLnet-funded projects to create an innovative SoC to validate the toolchain.

By delivering these tasks, the project will support the LiteX ecosystem, encourage innovation, and share the outcomes within the open-source hardware community.

>> Read more about LiteX

lpnTPM — TPM 2.0 compliant open hardware Trusted Platform Module

lpnTPM is Open Source Software (OSS), and Open Source Hardware (OSHW) Trusted Platform Module (TPM, also known as ISO/IEC 11889) is an international standard for a secure cryptoprocessor, a dedicated microcontroller designed to secure hardware through integrated cryptographic keys. What makes lpnTPM different from generally available solutions is openness. Software and hardware of lpnTPM can, without limits, be audited, fixed, and customized by communities and businesses. Open design address the lack of trustworthiness of proprietary closed source TPM products, which currently dominate the whole market. lpnTPM in production mode protects software by secure boot technology, and only the lpnTPM owner will update it. TPM modules enable measured boot and support verified boot, Dynamic Root of Trust for Measurement, and other security features. Another benefit of lpnTPM would be physical design, which solves the lack of standardization around pinout and connector. The ultimate goal of lpnTPM is to provide a trustworthy platform for future open evolution of Trusted Platform Module software and its application to various computing devices, resulting in better adoption of platform security.

>> Read more about lpnTPM

LunaPnR Phase 2 — A versatile and fast new open-source place and route tool

Making a custom chip (ASIC) requires a vast arsenal of tools, to do synthesis, simulation, parasitic extraction and schematic entry. . LunaPnR aims to add a robust open-source automated place & route tool to the equation. Luna targets ASIC processes larger than 100nm, in which it can perform place & route, do clock-tree synthesis and timing verification. This allows to design e.g. mixed-signal (analogue + digital) chips used in sensors and IOT devices. LunaPnR integrates well with existing open-source tools, such as YosysHQ's Yosys (a logic synthesis tool) and KLayout (a manual ASIC layout tool), but also with commercial tools via industry standard file formats (LEF, DEF and GDS). A fully open toolchain allows for a complete chain-of-trust between the chip designer and the chip manufacturer, from digital design to GDS2 and back (via wafer inspection).

In this new project LunaPnR will implement and test detail routing algorithms, enhancing the quality of the parasitic extraction for use with the OpenSTA static timing analyzer, speed up the graphical user interface (so it can render very large design efficiently), implement and test the power structure/special net/padring placer & router, and integrate Logic Equivalence Check (LEC).

>> Read more about LunaPnR Phase 2

Machdyne — Modular open compute hardware

Machdyne designs and builds small computers intended for timeless applications such as reading, writing, math, education, organization, communication, and automation. We are creating a new series of open-source computer designs based on European-manufactured FPGAs. These computers will use an updatable open-source System on a Chip (SoC) that can be fully audited, understood and trusted.

>> Read more about Machdyne

MEGA65 Phone — A phone simple enough to understand in full

Much of the insecurity and lack of privacy is the simple result of how complex computers, the internet and all of the protocols and technologies that they include. It seems that the majority of proposals to fix this solution consist of adding something to this complicated mess. While this has helped to reduce the symptoms of the problem, by adding complexity it has actually made the problem worse. There are simply too many places for insecurities and privacy violating software to hide in modern complex systems. Even the hardware itself is not immune, with problems like SPECTRE, MELTDOWN and vulnerabilities in the management processors of modern computers and phones showing that even the processors we use today carry significant risks due to their complexity. This project takes a contrarian approach of seeing just how simple a system can be make, that would still be useful for a core set of functionality. The project takes inspiration from the simple and effective computers of the 1980s: it explores how to retain their simplicity and transparency, and combine them with modern improvements in security and capability. The goal is to allow even a single determined person to completely verify that a device has not been compromised, and that there are no unwanted listening ears when performing privacy sensitive tasks. The project will advance its current proof-of-concept to a functioning hardware and software system that can demonstrate profoundly improved security and privacy, and in a way that allows a determined user to verify that the device is still truly under their exclusive control and serving them alone.

>> Read more about MEGA65 Phone

MEGA65 Phone Modular MVP — OSHW mobile device with form-factor of hand-held game consoles

The previous MEGAphone project laid the groundwork for creating personal communications devices that are secure through simplicity. This project extends that work by making the hardware modular, at some cost of minimum size, so that it becomes much more feasible for small communities to produce and maintain their own units, even in the face of supply chain challenges and other contributors to the "digital winter", i.e., the situation where open innovation becomes more difficult due to number of factors. This will also make it easier to include diverse resilient communications options, whether RF, optical or acoustic, so that peer-to-peer communications networks can be sustained even in environments that are hostile to freedom of communications. For this reason energy sovereignty will also be part of the design, so that even if all civil infrastructure is denied, that basic communications and computing functions can be sustained, with a single device whose security can be much more easily reasoned about.

>> Read more about MEGA65 Phone Modular MVP

mikroPhone — Open Hardware feature phone

mikroPhone is currently a basic feature phone with extensible open source firmware. It is a fully open hardware device and it can easily be built in a home lab. It is intended to protect user's privacy to the highest possible level and to bring data sovereignty back to its users.

This project focuses on further improvement of the basic phone device and integration of ARM module that runs GNU/Linux OS. Since linux module is entirely optional, it is not used for handling any critical functions of the device (e.g. cellular voice and secure VoIP calls, SMS messaging) and it can be powered-up on demand. This would solve common problems of linux smartphones such as poor basic phone functionality and short battery life. The goal of the project is to provide an option of enjoying a fully usable linux smartphone.

>> Read more about mikroPhone

MNT Reform — A trustworthy open hardware laptop

MNT Reform is a modular open hardware laptop, the first of its kind - designed and built in Europe. The project has high ambitions in terms of usability and user experience. A mechanical keyboard and an elaborate industrial design provide for professional ergonomics. MNT Reform uses RISC processors like ARM and has no built-in recording technology. It runs a free and open source software stack from the ground up. Third parties can easily contribute to the development of new modules. The modular approach does not only make the laptop more extensible but also improves sustainability, and supports the right to repair.

During the project, the team will develop two open hardware System-on-Modules. The first module is based on NXP LS1028A, and will increase RAM capacity to up to 16GB and make external GPUs usable. The second open hardware SoM uses an FPGA (field programmable gate array) to support the validation of open silicon SoC projects in a real laptop. Modules like this make the development of embedded computers easier for open hardware engineers by pre-solving risky and expensive challenges. Finally, we will develop an optional camera module for MNT Reform as part of the project, which will allow the laptop to be used for remote learning and video conferencing.

>> Read more about MNT Reform

MNT Reform Next — New iteration of the MNT open hardware laptop

MNT Reform Next is a new, thinner and higher performance version of the renowned Open Hardware laptop MNT Reform. It adopts connectivity standards like USB-C and PD charging, remains modular and aligned with the Right to Repair, and is built with longevity in mind. The project aims to bring Open Hardware computing and Free and Open Source Software to a larger audience by lowering cost and increasing portability while delivering more processing power.

>> Read more about MNT Reform Next

Caster — Open-hardware high-refresh-rate electrophoretic display controller

Modos is building an libre, open source and open hardware ecosystem of low-cost, affordable electronic devices that use an E Ink display and are driven by the first open-hardware high-refresh-rate electrophoretic display controller of our own design. Having such a controller will enable the creation of new devices and applications designed around the advantages of this dynamic medium: easier on the eyes, less power consumption, readable in direct sunlight, and persistence.

In this project, the team will incrementally improve upon the existing (working) prototypes and establish a Pilot Program . The team provides community support, and makes sure you contribute to the development of the open hardware ecosystem.

>> Read more about Caster

Mosaic — Trustworthy open hardware design tool for electrical engineers

Today, the chip design industry is deeply proprietary with NDAs at every level, which means it is not possible to share design files at all, which in turn stifles innovation and transparency in chip design. In order to create a chip design industry that can be trusted with our digital lives, and is accessible to educational institutions and small business, it is essential to develop powerful open source tools for chip design, which can be used by anyone and allows unhindered collaboration. Mosaic is a tool that attacks the first design phase of an analog chip, or analog peripherals for a digital one: design and simulation of the schematic. It will also interact with other phases of the design as needed. Unlike existing open source solutions it will be catered towards chip design, based on modern technologies, and extensive UX design.

>> Read more about Mosaic

Test Procedures for MOSFET Open Source SPICE Model Validation — Test Procedures for MOSFET SPICE Model Validation

The emergence of open PDK initiatives reduce barriers to entry for integrated circuit (IC) design and manufacturing, serves thelong term goal of promoting academic/industrial collaboration, and stimulate innovation in the field of semiconductor IC design. Open PDKs have the potential to "standardize" PDKs (process design kit), and move away from proprietary/licensed EDA vendor formats. This is needed to democratize open source IC design flow and manufacturing. Open PDKs provide open access to IC design resources.

The compact/SPICE models of semiconductor devices are the core of open PDK efforts. SPICE executes implemented Verilog-A compact models. A model of a semiconductor device (passive elements and active, eg: diodes, mosfets, bjts) is primarily a "compact device model". Validation benchmarks are not yet available in the public domain. This project represents the very first attempt to implement these tests for the compact model available in open PDKs. It aims to establish such tests for the compact models in open PDKs, which are intended to be generic enough for model quality assurance testing with FOSS circuit simulators such as GnuCAP, ngspice, xyce, Qucs, among others.

>> Read more about Test Procedures for MOSFET Open Source SPICE Model Validation

Naja — EDA tool focused on post logic synthesis

Naja is an EDA (Electronic Design Automation) project aiming at offering open source data structures and APIs for the development of post logic synthesis EDA algorithms such as: netlist simplification (constant and dead logic propagation), logic replication, netlist partitioning, ASIC and FPGA place and route, …

In most EDA flows, data exchange is done by using standard netlist formats (Verilog, LEF/DEF, EDIF, …) which were not designed to represent data structures content with high fidelity. To address this problem, Naja relies on Cap'n Proto open source interchange format.

Naja also emphasizes EDA applications parallelization (targeting in particular cloud computing) by providing a robust object identification mechanism allowing to partition and merge data across the network.

>> Read more about Naja

Naja DNL — Add Dissolved and Batch Netlists to Naja EDA

Naja is an EDA (Electronic Design Automation) project aiming at offering open source data structures and APIs for the development of post logic synthesis EDA algorithms such as: netlist simplification (constant and dead logic propagation), logic replication, netlist partitioning, ASIC and FPGA place and route, … In most EDA flows, data exchange is done by using standard netlist formats (Verilog, LEF/DEF, EDIF, …) which were not designed to represent data structures content with high fidelity.

To overcome this problem, Naja relies on Cap'n Proto open source interchange format. Naja also emphasizes EDA applications parallelization (targeting in particular cloud computing) by providing a robust object identification mechanism allowing to partition and merge data across the network.

The core of Naja is formed by two interrelated data structures: the Structured Netlist (SNL) and the Dissolved Netlist (DNL). SNL is tailored for high-fidelity representation of hierarchical netlists, while DNL offers a flattened netlist view, optimized for rapid, multi-threaded analysis and optimization tool development.

>> Read more about Naja DNL

NaxRiscv core improvements — Open hardware out-order Risc-V CPU

This project aims at extending the scope of the NaxRiscv project (a free and open-source out-of-order multi-issue RISC-V CPU, using innovative hardware description technics and optimized for FPGA deployment) by getting the CPU to run Debian in a stable manner and documenting the whole process used to build the required binaries/rootfs, implementing memory coherency, multicore support and a L2 cache to enhance the performances, and finally, optimizing and synthesizing the CPU for ASIC using the free and open-source tooling to pave the way for some future NaxRiscv based silicon chips.

>> Read more about NaxRiscv core improvements

nextpnr for GW-5 — Add support to nextpnr for Gowin GW-5 FPGA family

This project focuses on enhancing the open-source FPGA design toolchain (specifically nextpnr and Apicula), to support the Gowin GW-5 series of FPGAs. This initiative involves creating detailed documentation and developing tools to understand and utilize these FPGAs effectively. By extending nextpnr and Apicula to generate valid bitstreams for the GW-5 series, the project aims to make advanced FPGA technology more accessible and usable for designers and engineers around the world.

>> Read more about nextpnr for GW-5

Nitrokey — Open hardware for encryption and authentication

Nitrokey is an open source hardware USB key for data encryption and two-factor authentication with FIDO. While FIDO is supported by web browsers, using Nitrokey as a secure key store for email and (arbitrary) data encryption requires a native software. Therefore email encryption in webmail isn’t possible with Nitrokey. At the same time strong end-to-end encryption in web applications all share the same challenge: To store users' private keys securely and conveniently. Therefore secure end-to-end encryption usually requires native software too (e.g. instant messenger app) or - less secure - store the user keys password-encrypted on servers. Nitrokey aims to solve these issues by developing a way to use Nitrokey with web applications. To avoid the necessity of device driver, browser add-on or separate software this project is going to utilize the FIDO (CTAP) protocol. As a result the solution will work with any modern browser (which all support WebAuthn), on any operating system even on Android. This will give any web application the option to store private keys on ones own Nitrokey devices.

>> Read more about Nitrokey

Nitrokey 3 — PIV/FIPS 201-3 and extended hardware support for Trussed/Nitrokey

Nitrokey 3 is an open source hardware USB/NFC key aiming for data encryption and two-factor authentication. Currently it supports FIDO2 authentication and WebCrypt. This project will allow it to extend its Rust firmware, developing additional functionality which makes it into a full-featured open hardware security key. By adding support for new so called 'secure elements' to Trussed, any device using Trussed can benefit from more hardware options. Within the project we will also develop PIV support for Nitrokey 3. PIV is a smart card standard which is used in enterprises and also popular among users of some operating systems like Microsoft Windows. PIV allows for data encryption, signing and authentication.

>> Read more about Nitrokey 3

Trussed — Open hardware for encryption and authentication

The project summary for this project is not yet available. Please come back soon!

>> Read more about Trussed

O-ESD: Open-hardware for ElectroStatic Discharge testing — Open-hardware for ElectroStatic Discharge testing

The goals of the Open-hardware for ElectroStatic Discharge testing (O-ESD) is to design, produce and verify an open-hardware and accompanying open-software for a device for electrostatic discharge testing. Electrostatic discharge is a phenomenon that occurs daily between humans and electronics and can irreversibly damage the electronics. All consumer electronics sold in EU, including all internet hardware, must satisfy Electromagnetic Compatibility (EMC) Directive. One of the most hardest tests within EMC directive deals with electrostatic discharge as defined by IEC/EN 61000-4-2 standard. Standardized tests are typically done with special equipment in accredited EMC laboratories and are costly. The O-ESD tester will minimize the costs of pre-compliance testing and make it publicly available.

>> Read more about O-ESD: Open-hardware for ElectroStatic Discharge testing

Open Know-How Search — Search Open Hardware Projects

Open Know-How Search is a project to create a search engine for the open source hardware designs. We are building a modern, clean and accessible search experience for makers. Our index will span the entire internet and all existing ways to share designs. Users and platforms will be able to make use of the Open Know-How meta-data standard to help get their projects into the index and surface those that are in advanced stages of development and worth looking at and attempting to re-build. The front page and top results in the search will be a useful resource to someone looking for a new open source hardware project to build and contribute to.

>> Read more about Open Know-How Search

openCologne — CM4 form factor SoM for GateMate chips

Currently there are few FGPA vendors in Europe. One of these vendors, CologneChip, produces the GateMate chips which have some high quality features compared to other FPGA's, such as a high speed SerDes. Recently we have seen the appearances of a number of affordable boards with these FPGA's. The challenge (and opportunity) is now to make sure that the open hardware community can benefit from these FGPA's as soon as possible.

This project will design a new iteration of the popular open hardware ULX-boards (ULX5M) featuring GateMate chips, which will be compatible with the widely used CM4 form factor - so it can be slotted into many existing designs instantly. This opens up this strategic new FPGA target for a broader audience, and help breach the market. In addition, the project will make a portfolio of entry level projects that selectively put GateMate resources to good use, including its unique SerDes. Be they in RTL or HLS, implemented as pure hardware FSMs, or by using HW/SW co-design and SOC techniques, or integrated with LiteX - delivering a variety of real-life use cases.

>> Read more about openCologne

OpenCryptoHW — CGRA- based reconfigurable open-source cryptographic IP cores

OpenCryptoHW aims to develop reconfigurable open-source cryptographic hardware IP cores for Next Generation Internet. With the Internet of Things (IoT) upon us, security and privacy are more important than ever. On the one hand, if the security and privacy features are exclusively implemented in software, the risk of breaches is high. On the other hand, if implemented solely in hardware, it is impossible to fix bugs or deploy critical updates, which is also a threat to security and privacy. Hence, we propose to use reconfigurable hardware, providing the flexibility of software and the trustworthiness of hardware. Hacking into it requires first hacking the device’s configuration infrastructure and then hacking the algorithm itself, which is way more complicated. There have been proposals to implement cryptographic IP cores using Field Programmable Gate Array (FPGAs). However, the FPGA configuration infrastructure is cumbersome and proprietary, increasing device cost and compromising safety. Therefore, we propose to use open-source Coarse-Grained Reconfigurable Arrays (CGRAs) instead of FPGAs. CGRAs have much lighter configuration circuits and are not controlled by any private entity. With OpenCryptoHW, hardware and system designers will be able to download CGRA-based cryptography IP cores for free and under a permissive license, ready to integrate into their silicon designs.

>> Read more about OpenCryptoHW

OpenCryptoLinux — Make Linux run on OpenCryptoHW

OpenCryptoLinux aims to develop an open, secure, and user-friendly SoC template capable of running the Linux operating system, with cryptography functions running on a RISC-V processor. The processor will control a low-cost Coarse-Grained Reconfigurable Arrays (CGRAS) for enhanced security, performance, and energy efficiency. Running Linux on this SoC allows non-hardware experts to use this platform, democratizing it. This project will help build an Internet of Things (IoT) that does not compromise security and privacy. The project will be fully open-source, which guarantees public scrutiny and quality. It will use other open-source solutions funded by the NLnet Foundation, such as the RISC-V processors from SpinalHDL and the OpenCryptoHW project.

>> Read more about OpenCryptoLinux

OpenCryptoTester — System-on-Chip for hardware/software testing

This project aims to develop a System-on-Chip (SoC) used mainly to verify cryptographic systems that improve internet security but can also be used on any SoC. It is synergetic with several other NGI Assure-funded open-source projects – notably OpenCryptoHW (Coarse-Grained Reconfigurable Array cryptographic hardware) and OpenCryptoLinux. The proposed SoC will support test instruments as peripherals and use OpenCryptoHW as the System Under Test (SUT), hopefully opening the way for open-source test instrumentation operated under Linux.

>> Read more about OpenCryptoTester

DRTM implementation for AMD processors — Unified framework for dynamic RTM

The Trenchboot project aims to create a unified framework for dynamic RTM (DRTM) implementation for all platforms. (D)RTM is used to verify if bugs or vulnerabilities have compromised a system, and as such is an important component to get to advanced stages of trustworthiness for our hardware.

>> Read more about DRTM implementation for AMD processors

OpenEMSH — Automatic mesher for FDTD simulation

OpenEMS is arguably the only free and open source FDTD solver out there that is usable out of the box for RF (Radio Frequency electromagnetics) design. Its main competitive disadvantage is that FDTD requires simulated models to be meshed according to specific rules, yet it does not provide an automatic mesher to create such meshes. Some facilities already do exist but meshing by hand is time-consuming and error-prone - enough to stand in the way of broader adoption. OpenEMSH aims to be a mesher for OpenEMS that makes it as simple to use as any proprietary solution.

>> Read more about OpenEMSH

Open Energy Profiler Toolset — Modular open hardware Energy Profiling

Battery-powered devices often incorporate high-speed communication protocols that consume power in high peaks. One of the main challenges is to provide a compatible set of hardware and software solutions that will enable easy and high-precision energy profiling tools which enable high-speed sampling rates and high current rates.Energy consumption profiling of such devices requires the use of various hardware and software solutions that are often not compatible, making them difficult to use, or do not provide suitable measurement accuracy. Our primary objective is to provide a unified toolset that encompasses an EEZ bus compatible hardware platform, open-source firmware, customized protocols for external firmware energy debugging, and a user-friendly graphical interface for widely used operating systems like Windows and Linux. This toolset will enable the end user to quantify overall MCU-based device consumption and identify energy-intensive software parts within an IoT end device. The project outcomes will include an EEZ Bus compatible standalone acquisition card that support sampling data rates up to 4 MSPS and high-speed data streaming through an Ethernet interface; an open-source library as support for energy debugging of end device firmware; and open-source GUI application for visual examination of different energy consumption parameters.

>> Read more about Open Energy Profiler Toolset

openPCIe2 Root Complex — Open hardware implementation of gen 2 PCIexpress in OpenXC7

This project will develop an open hardware implementation of PCIexpress 2.0, the high-speed serial computer expansion bus standard used to allow computer peripherals to be slotted into a motherboard. When designing open hardware, having such a critical part of a component depend on proprietary components is obviously . The open hardware PCIe/Gen2 Root Complex developed within this project would make a big step towards developing fully open hardware components. Prior efforts only provided a partial implementation, and depended on vendor-provided 'black boxes' that would prevent such designs to be used to create a working, fully open hardware solution.

>> Read more about openPCIe2 Root Complex

OpenQRNG — Open source, certified Quantum Random Number Generator

Cryptography is key to protecting our modern secrets, and random numbers form the basis of the technical assurances given by that approach. However, true randomness is hard to achieve. Quantum number generators lever unpredictable physical phenomena to deliver quality randomness, and as such can be of great utility. However, currently there are only proprietary QRNG sources with a significant price tag - which means that the technology is not widely in use and that those people that do have the means have to essentially trust the vendor in question. The project will develop an open hardware QRNG device, which can be inspected from top to bottom - and made available at low cost.

>> Read more about OpenQRNG

openwifi: 802.11a/g/n maturity — Improved stability, data rate and reach of openwifi

Wi-Fi has become ubiquitous in modern society. While many people might assume that the Wi-Fi chip in AP, mobile devices, and computers is a dumb device that merely sends and receives packets over the air, the reality is far more complex. Even the most affordable Wi-Fi chips are sophisticated heterogeneous computing systems, as highlighted by many researchers and hackers. These chips contain multiple types of firmware and silicon fabric working together. The lack of open-source Wi-Fi chips and the transparency of commercial Wi-Fi chips have raised many security concerns: The security threats over Wi-Fi have emerged for years. Openwifi (https://github.com/open-sdr) aims to address this issue. It is the first open-source soft-MAC Wi-Fi chip/FPGA design, initially released at the end of 2019, with 802.11n added in 2020. As more users, researchers, and hackers engage with the project, they have identified issues related to stability, data rate, and communication distance. This maturity-elevating project aims to tackle these issues through improvements in the Linux driver, FPGA, and RF control. The enhanced version will be comparable to commercial Wi-Fi4 chips, such as the ath9k series, and will be capable of operating in more realistic electromagnetic environments rather than just short-range, controlled environments. These advancements will facilitate broader adoption of the project and lay a solid foundation for future developments, including the creation of a real chip.

>> Read more about openwifi: 802.11a/g/n maturity

openXC7 — Improve hardware support for open source FPGA tooling

FPGAs are reconfigurable chips capable of handling many electronic signals in parallel. They are used in network equipment like backbone switches, firewalls, video devices like surveillance cameras and radio equipment like mobile-phone base stations, radar systems and satellites to process high volumes of data with very low latency. FPGAs are also used to test digital circuit designs before they are manufactured as chips.

The functionality of FPGAs is determined by a configuration file which is loaded into the FPGA at power-on. The configuration file is usually generated from a design file by a proprietary tool provided by the manufacturer of the FPGA.

openXC7 will provide a complete set of open source tools to generate a configuration file for the widely used family of Xilinx Series 7 FPGAs from manufacturer Xilinx/AMD without having to use any proprietary tools. This will empower digital design engineers to have the guarantee that no backdoor is implemented on FPGA based devices by the proprietary design tool provided by the vendor.

The availability of the source code of the FPGA design tool will also allow anyone to come up with new use cases for FPGAs currently not possible with existing tools.

In this project the team will implement gigabit transceiver support, both for the widely used Artix7 and the Kintex7 families of devices, thus enabling complete open source network infrastructure (e.g. an open source 10 GB Ethernet switch). The second focal point will be identifying and fixing issues that arise from the community of users of the toolchain.

>> Read more about openXC7

S-SATA for openXC7 — Open source SATA phy and interface for FPGA's

This project develops an open-source SATA controller for use with FPGA technology, specifically targeting the Xilinx Kintex/Artix7 family. SATA, which stands for Serial Advanced Technology Attachment, is a technology used to transfer data between a CPU and an attached persistent storage device. By creating an open-source hardware controller, this project will make it easier and more affordable for researchers and developers to implement dependable high-speed data storage solutions in their FPGA-based projects. Initially, the controller will support the 1500Mb/s data transfer speed typical of earlier SATA versions. Our development plan includes both building this controller, a hardware simulation of it, and software to demonstrate it. We then intend to implement it on actual hardware and prove it works.

>> Read more about S-SATA for openXC7

Ordie — Designing a SoC for Betrusted

The field of open silicon is still in its infancy, and while the story on digital logic generation is good, analogue is still a work in progress, and full system integration is only just beginning. The Ordie project will characterize available analogue and digital blocks, integrate them, and create simulation and test software to validate them both pre- and post-production. In this way, the Ordie project will create open, fully-verified silicon chips where every aspect of the part is inspectable down to the raw GDS files. These parts will be usable in some aspects of projects such as Betrusted, where they may be used to replace some of the proprietary silicon with open variants. Along the way it will develop a circuit that enumerates over USB, be able to address various debug structures using existing Wishbone USB and Spibone debugging, and develop a buck regulator, useful for powering on-die structures.The on-chip blocks will be documented using reference systems such as lxsocdoc.

>> Read more about Ordie

OVT 13 — Open Hardware laptop

The open hardware laptop OVT 13 (Open Vision Technology 13" Laptop) will be a thin and light laptop that is on-par in terms of performance and look-and-feel with established solutions available from market dominating competitors. The OVT 13 is designed to meet the modern standards imposed on thin and light laptops. The fully open-hardware design as well as the modular approach will satisfy both the enthusiast and non-technical user in terms of design openness, upgradability and repairability, performance and formfactor.

The vast amount of engineering innovation that goes into designing consumer electronics devices goes unnoticed by many users. These innovations take place behind closed doors and do not advance the technical progress of our society, but only serve to increase the market share of a single company. The OVT 13 will not only be an open hardware design, but also a communication effort that shines a light on the design challenges and the innovations needed to overcome them. By publicly documenting the whole design process no knowledge will be kept behind closed doors and the innovation that goes into designing such a system can be used by everyone.

>> Read more about OVT 13

Patchouli — Arbitrary-sized open hardware EM pen products

Patchouli is an open-source electro-magnetic drawing tablet hardware implementation, including a coil array, an RF front end built using commercially available parts, and digital signal processing algorithms. The design is compatible with most commercial pens from different vendors, offering an ultra-low-latency pen input experience for your customized hardware projects. The hardware is released under the CERN-OHL-S license, and the firmware/simulation code is released under the GPL3+ license.

>> Read more about Patchouli

pcb-rnd — Modular printed circuit board editor

Pcb-rnd is a modular printed circuit board editor that is designed with the UNIX mind set. It has a convenient GUI for editing the graphical data of the board but is also has a handy command line interface. Both the GUI and the CLI aspects are scriptable (in more than 10 scripting languages) and pcb-rnd can also process boards as a headless converter tool. It has support for various proprietary schematics/netlist and board formats which makes it also a good choice for converting free hardware designs coming in proprietary formats to free file formats. Among the upcoming challenges are a full rewrite of the Design Rule Checker, more file format support and making the menu system even more dynamic to match the modular nature of pcb-rnd better.

>> Read more about pcb-rnd

Securing PLCs via embedded protocol adapters — Open hardware protocol adapters for industrial automation

Industrial Programmable Logic Controllers have been controlling the heart of any production machinery since the mid-70s. However have these devices never been built for the usage in completely unprotected environments such as the Internet. Currently most PLCs out in the wild have absolutely no means to protect them from malicious manipulation (Most don't even have an effective password protection). Unfortunately "Industry 4.0" is all about connecting these devices to the Cloud and hereby attaching them to potentially unsecure networks. In the "Securing PLCs via embedded Open-Source protocol adapters" initiative we are planning on porting the Apache PLC4X drivers to languages that can also be used in embedded hardware. Additionally we also want to create secure protocol-adapters using these new drivers together with Apache MyNewt, to create protocol-adapters that could eventually even be located inside the network connectors which are plugged into the PLC in an attempt to reduce the length of the unsecured network to an absolute minimum without actually modifying the PLC itself.

>> Read more about Securing PLCs via embedded protocol adapters

PTP gateware with openXC7 — PTP on FPGA timing cards and SDR cards with openXC7

This project develops open-source gateware for the Precision Time Protocol (PTP), which is essential for accurate timekeeping across servers. Implementing this technology on Xilinx ZYNQ FPGA chips, it offers a secure, reliable alternative to proprietary gateware, reducing the risk of undetected security breaches through server backdoors. This initiative not only enhances Internet security but also enables diverse applications, from 5G networks to research instruments like particle accelerators, making advanced time synchronization accessible, and safeguarding the digital ecosystem for the general public.

>> Read more about PTP gateware with openXC7

Py2HWSW — A tool to manage embedded HW/SW project

This project aims to develop an open-source Python framework for managing files, automating project flows of embedded hardware/software codesign projects, and partially generating Verilog hardware components. The framework simplifies the project structure, addresses challenges in Hardware Design Languages like Verilog and VHDL, and automates emulation, simulation, FPGA, and ASIC flows. The proposed Verilog generator offers flexibility, user control and ease of use, producing human-readable code compatible across FPGAs and ASICs.

>> Read more about Py2HWSW

Radio-Meshnet — Self-sustained Community and Emergency Radio Networking

The project summary for this project is not yet available. Please come back soon!

>> Read more about Radio-Meshnet

RAIJIN — Open Hardware brain measurements with near-infrared spectroscopy

Low-cost electroencephalographic (EEG) systems have been available for over a decade, such as the open hardware OpenBCI ecosystem. While EEG has been democratized to varying degrees, blood-oxygen-level-dependent (BOLD) methodologies are constrained to medical and niche realms. While magnetic resonance imaging is impractical for a hobbyist, functional near-infrared spectroscopy (fNIRS) may offer a more practical alternative. Similarly, non-visual and non-auditory feedback from a brain-computer interface (BCI) may be streamlined with a tactile or haptic device. Transcranial temporal interference stimulation (TTIS) can be directed and integrated with the existing ecosystem. The Rank-Adjusted Infrared Juxtaposed Interferential Neuromodulation (RAIJIN) marks three components that would significantly improve tools for citizen-scientists. Given recent low-cost projects, it may be possible to bring low-cost fNIRS, non-invasive deep brain stimulation, and tactile response into the OpenBCI ecosystem. Tactile and TTIS enable closed-loop computer-brain interference (CBI). By integrating BCI and CBI, the RAIJIN system will enable mobile, low-cost, BOLD-capable, closed loop, and non-invasive brain-to-brain interface (BBI).

>> Read more about RAIJIN

RA-Sentinel — FPGA-based Radio Receiver for securing Wifi against hacking attacks

The proposed project aims to develop a cost-effective, small, and low-power wide band radio receiver device that automatically detects various malicious attacks on Wifi access points, such as Man in the Middle and Denial of Service attacks. The RA-Sentinel project is designed to protect your home WiFi from unwanted cyber threats. Think of it as a digital watchdog for your internet connection that barks when someone from the outside tries to break in. The device will enhance internet safety for ordinary users by monitoring any Wifi cell. It will consist of low-cost receive-only chips that digitizes 40 MHz of the Wifi radio spectrum at 2.4 GHz and extracts with the FPGA relevant properties from demodulated and decoded packets in real-time without storing them. These properties are fed into a neural network also implemented on an FPGA, which determines if the traffic is genuine or an attack. Only open source FPGA tools will be used.

>> Read more about RA-Sentinel

Real Time Litex Extension — Real time capabilities for FPGA-based RISC-V core

The Core-Local Interrupt Controller (CLIC) is a RISC-V standard extension that enhances real-time performance by enabling the prioritization of interrupts based on levels and priorities. This feature allows developers to have fine-grained control over interrupt prioritization, leading to more efficient handling of real-time events. In this project, we propose to replace the original interrupt controller of the VexRiscv based processor core family with CLIC. By implementing the CLIC, VexRiscv can efficiently propagate the highest-level, highest-priority pending interrupt to the core, significantly improving real-time responsiveness. The CLIC implementation also introduces features like selective hardware vectoring and the special register (xnxti CSR), which further optimize interrupt handling.

>> Read more about Real Time Litex Extension

Redox Flow Battery — Development Kit for Open-Source Hardware Redox Flow Battery

The clean energy transition is underway, and batteries are becoming more common in everyday life. Stationary batteries can perform many roles, like reversibly storing intermittent renewable energy or providing backup power and services to the electrical grid, including internet infrastructure. Right now, lithium-ion batteries—also used in portable electronics and electric vehicles—are increasingly used for stationary applications. Lithium-ion batteries are, however, not ideal in terms of lifetime, cost, safety, and supply chain sustainability. There are viable alternatives to lithium-ion batteries for stationary storage, such as flow batteries, which are being commercialized but are not yet widespread. We plan to democratize flow battery technology by developing an open-source flow battery and starting an associated community around it. We will start with a benchtop-scale development kit, suitable for educational and research use, before progressing towards larger cells. With this NLnet funding, we plan to finish our first release of a 5 cm² kit as well as design and test the subsequent 25 cm² cell.

>> Read more about Redox Flow Battery

pcb-rnd, sch-rnd — Open source EDA suite

Ringdove EDA is a modular, portable Electronics Design Automation toolkit mainly targeting the Printed Circuit Board design workflow. The two flagship projects in Ringdove are sch-rnd (schematics capture) and pcb-rnd (printed circuit board editing). Because of the modular layout of the code and the active management of dependencies, both projects are highly portable, both in time (old, present and future systems) and in workflows (interactive graphical design or interactive command line usage or headless automated processing). Ringdove also strives to support file formats of other EDA software, especially for loading proprietary formats, making existing/legacy hardware designs more accessible to the Open Source community.

>> Read more about pcb-rnd, sch-rnd

RISC-V Phone — Open hardware RISC-V Phone

The goal of the "RISC-V Phone" project is to develop a simple, fully featured and privacy enhanced mobile phone. It is built using off-the-shelf inexpensive components which are easy to assemble even in a home lab. The software for it is small, simple and easy to audit. Basic phone functionality is running on a secure RISC-V microcontroller (FE310 from SiFive) which controls all peripherals: microphone, speaker, display/touch controller, camera. The phone will be using esp32 for WiFi and Bluetooth, along with industry standard mPCIe modem for cellular communication. Graphics/touch panel controller FT813 enables advanced user experience. The phone will provide VOIP/messaging application using packet data protocol similar to CurveCP which features end-to-end encryption and onion routing. There is also a socket for optional ARM SoM which shares display/touch panel with the main board.

>> Read more about RISC-V Phone

SpinalHDL, VexRiscv, SaxonSoc — Open Hardware System-on-Chip design framework based on SpinalHDL

The goal of SaxonSoc is to design a fully open source SoC, based on RISC-V, capable of running linux and optimized for FPGA to allow its efficient deployment on cheap and already purchasable chips and development boards. This would provide a very accessible platform for individuals and industrials to use directly or to extend with their own specific hardware/software requirements, while providing an answer to hardware trust.

Its hardware technology stack is based on 3 projects. SpinalHDL (which provides an advanced hardware description language), VexRiscv (providing the CPU design) and SaxonSoC (providing the facilities to assemble the SoC).

In this project, we will extend SpinalHDL, VexRiscv and SaxonSoc with USB, I2S audio, AES and Floating point hardware capabilities to extend the SoC applications to new horizons while keeping the hardware and software stack open.

>> Read more about SpinalHDL, VexRiscv, SaxonSoc

scalePNR — New place and route algorithms for large FPGAs

The scalePNR project focuses on enhancing digital circuit design for large Field-Programmable Gate Arrays (FPGAs), which are complex chips used in everything from consumer electronics to mobile phone base stations to cameras to AI accelerators to internet backbone infrastructure to advanced computing systems. Traditionally, designing these chips has been a highly specialized and time-consuming task, due to the complexity and computational demands of arranging and determining efficient wiring between the millions of tiny logic blocks they contain.

The goal of this effort is to tackle larger, more advanced FPGAs and make the process of designing circuits for these high-capacity chips more accessible and efficient, potentially leading to faster, more energy-efficient electronic devices. By researching and implementing new algorithms, the project aims to make it easier and quicker to design circuits that run cooler, faster, and more reliably, bringing the benefits of the latest technology to a broader audience and fostering innovation in numerous tech-driven sectors.

>> Read more about scalePNR

SDCC — Small Device C Compiler compiler for 8-bit microcontrollers

The Small Device C Compiler (SDCC) is free and open source software for 8-bit microcontrollers. While such 8-bit microcontrollers might seem like outdated technology (most of the popular chips sold today use 32 bit or 64 bit solutions), the fact that there are less transistors to fire up with every cycle means there are quite a few basic use cases where 8-bit systems might very well remain the most energy-efficient option despite . SDCC is competing head to head with various proprietary compilers - such as Keil, IAR, Comsic, Raisonance. The tasks in this project will significantly boosts the capabilities of SDCC and allow developers a more mature tool to design for e.g. eco-friendliness. The project will deliver various improvements in SDCC, in order to make it more complete and competitive in terms of features and workflow.

>> Read more about SDCC

SiCl4 — Tool for interactive reverse engineering of digital logic.

SiCl4 (silicon tetrachloride) is a tool for reverse-engineering digital logic designs. Starting from an FPGA bitstream or other types of netlists, this tool will assist users in interactively recovering higher-level structures. Algorithms will help with tasks such as finding shared subcircuits or identifying known patterns such as adders, counters, comparators, state machines, etc., so that the user can focus on understanding the higher-level functions of the target design. SiCl4 will be scriptable in order to allow for easy extension, and it will also integrate with the existing open-source EDA ecosystem.

>> Read more about SiCl4

Silicon verification — Non-destructive, in-situ inspection of physical chips

The global nature of supply chains presents an existential question for the trustworthiness of hardware: how do I know the chips in my device are genuine and pristine? Trusted domestic fabs only solve a facet of the problem: after a silicon wafer leaves the fab, it criss-crosses the globe multiple times as it is packaged, tested, and assembled into an end user product, presenting a huge attack surface for post-fab substitutions and alterations. The "Silicon Verification" project lays foundations for high resolution end-user, direct, and non-destructive optical inspection of chips. Our research aims to create a set of techniques for hardware packages that fill the analogous role of "digital signature verification" for software packages: a ubiquitous method to establish trust in a package, after it has been delivered to the user.

>> Read more about Silicon verification

Simmel — A wearable contact tracing beacon/scanner

Simmel is a platform that enables COVID-19 contact tracing while preserving user privacy. It is a wearable hardware beacon and scanner which can broadcast and record randomized user IDs. Contacts are stored within the wearable device, so you retain full control of your trace history until you choose to share it.

The Simmel design is open source, so you are empowered to audit the code. Furthermore, once the pandemic is over, you are able to recycle, re-use, or securely destroy the device, thanks to the availability of hardware and firmware design source.

The contact tracing algorithm is programmed using CircuitPython, to facilitate ease of code audit and community participation. The Simmel project does not endorse a specific contact tracing platform, but it is inherently not compatible with contact tracing proposals that rely on the constant upload of data to the cloud.

>> Read more about Simmel

Spade — Standalone Hardware Description Language

Spade is a hardware description language that draws inspiration from modern software languages to make hardware development more productive, more fun, and less error-prone. A big part of what makes this possible is the type system which helps prevent bugs and makes the code more maintainable.

A common source of errors in hardware designs is clock domain crossing: signals should never cross domains accidentally, and when they do cross, it must be done correctly. Failures to correctly cross domains leads to intermittent problems that can take significant effort to find and fix. By making the language and compiler aware of clock domains through the type system, we will be able to detect and warn programmers about accidental clock domain crossings at compile time. We will to do this in an ergonomic way, where the user only has to specify clock domains on module inputs and outputs with the compiler being able to infer the rest. In addition, the default case of a module that only spans a single domain should not require any explicit domain information form the user to avoid unnecessary verbosity.

>> Read more about Spade

Squishy — SCSI multi tool and gateware library

Squishy is a SCSI multi-tool aimed at long term access to computer systems and equipment. It accomplishes this by having capable hardware combined with an extremely flexible software ecosystem, allowing Squishy to act not only as nearly any device under the sun, but also as a SCSI bus initiator with high flexibility. Enabling it to be used for archival work to interact with obscure or arcane hardware to read magnetic tapes, or allowing modern systems to interface with and control older, but still reliable and used lab and scientific equipment. Squishy is currently in it's second prototyping phase, after lessons were learned from the first revision of the hardware. This involves a full redesign to grant it more capabilities and serve as a more solid foundation. The end goal is a relatively  small fully compliant device for multiple SCSI standards along with a robust software ecosystem, allowing for it to speak to any equipment be it a SCSI-1 tape drive, or an ULTRA-320 SCSI-based data acquisition system.

>> Read more about Squishy

Transitioning SMM Ownership to Linuxboot — More robust defense Against Firmware Vulnerabilities

In an era marked by escalating cybersecurity threats, firmware security is one of biggest blind spots. One pervasive weakness lies in an architectural design called System Management Mode (SMM). Sometimes referred to as “Ring -2”, SMM is used by device manufacturers to interact with hardware like NVRAM, emulate hardware functionality, handle hardware interrupts or errata, and perform other functions.

The unrestricted, non-standardized control inherent to SMM implies significant security vulnerabilities. There is no shortage of Day-0 and Day-1 Firmware vulnerabilities related to SMM. Current industry practices open a wide door for cyber attacks, and the attacker can even bypass the secured OS kernel with the SMM loopholes.

This proposal introduces a novel SMM architectural design, by transitioning SMM ownership from core firmware (e.g. coreboot) to payload - in this case Linuxboot. This will leverage the robust, open-source nature of Linux’s SMM drivers, as its drivers that has been proven working very well over decades, and its open source nature made it easier for security reviews. This initiative aims to develop and universalize a secure architectural design in collaboration with chip vendors, and thus elevating the resilience and integrity of our digital ecosystem.

>> Read more about Transitioning SMM Ownership to Linuxboot

Surfer Waveform Viewer — Analyse signal levels in simulated circuits

Surfer is an open source waveform viewer, primarily aimed at debugging digital designs. It is built for flexibility, extensibility, and speed to operate on most platforms. Although fully operational for many tasks, there are features to be added to improve the usability further. This project aims to implement the most requested missing features and pave a way for additional extensibility.

>> Read more about Surfer Waveform Viewer

Timing-Driven Place-and-Route (TDPR)  — Open hardware tool to synthesize digital silicon circuits

The lack of an open-source timing-driven place-and-route tool is one of the major barriers to creating technically fully transparent digital integrated circuits such as microprocessors. The most popular open-source place-and-route tools available today are not timing-driven, hence the generated layouts are generally not guaranteed to satisfy the timing constraints. This requires tedious and time-consuming manual interventions. This project will combine published algorithms with existing open-source projects to fill this gap. The tool will be released with the free/libre AGPLv3 licence together with extensive documentation and tutorials.

>> Read more about Timing-Driven Place-and-Route (TDPR) 

TerosHDL — Assisting hardware developers to deliver safer designs

TerosHDL is an open source IDE for FPGA/ASIC development. It includes a backend, a front-end built on VSCodium/VSCode and a command line interface. The goal of TerosHDL is make the ASIC/FPGA development easier and reliable: to reduce the adaptation time for new users of HW languages and help professionals.

TerosHDL is multi-platform (Linux, Windows, MacOS), multi language (VHDL, Verilog, SystemVerilog) and it takes advantages of a lot of open hardware projects (such as Edalize, WaveDrom, VUnit…), integrating them in a common graphical user interface. The IDE tries to be as much self-contained as possible and simplify the installation process.

Some of the features are: linter, go to definition, syntax highlighting, code formatting, snippets, automatic documentation, dependencies viewer, simulators support...

>> Read more about TerosHDL

TerosHDL: OSS, GHDL, NVC — IDE with support for Open SYthesis Suite and GHDL/NVC simulators

TerosHDL is an open-source graphical IDE tailored to FPGA/ASIC development. The goal is to empower engineers, hobbyists, and students to easily engage in RTL design, fostering innovation and growth in the field. TerosHDL serves as a comprehensive platform, supporting RTL design, synthesis, simulation and common code edition (linting, formatting, etc).

In this project, TerosHDL will incorporate support for a number of additional powerful RTL design tools: Yosys, GHDL, and NVC. This will give users an interface which is friendly to first time users, equipped with real-time feedback and debugging capabilities. This further streamlines the chip design process, enhancing efficiency and making RTL design more accessible and productive.

>> Read more about TerosHDL: OSS, GHDL, NVC

Tiliqua — Open audio DSP for FPGAs

Tiliqua is an open-hardware DSP library and reference hardware design which aims to make it easier for musicians and engineers to get started in the world of audio DSP in the context of FPGAs. The Tiliqua DSP library is a suite of commonly-used audio DSP components, written in Amaranth HDL, that can be easily composed in Python to construct a custom FPGA-based DSP pipeline. The Tiliqua reference platform is fully compatible with open-source FPGA toolchains and designed to the Eurorack standard (the most popular hardware synthesizer format) lowering the barrier to entry for those with low/no hardware development experience.

>> Read more about Tiliqua

TISG trustable image sensor gateware — FPGA based camera providing encrypted video streams

The TISG project is set to develop a groundbreaking open-source, FPGA-based camera system, focusing on the implementation of the MIPI-CSI2 standard for connecting a wide range of image sensors to FPGAs. The development process involves leveraging open-source FPGA tools and formal verification methods to ensure robust security and functionality. The primary purpose is to create a secure, versatile, and accessible video processing platform that addresses current security vulnerabilities in video-based systems. By eliminating reliance on proprietary software and enabling formal hardware verification, the project aims to significantly reduce the risk of backdoors and cyber threats. The general public will benefit from enhanced security in areas like home surveillance, public safety, and infrastructure monitoring. Additionally, the open-source nature of the project promotes innovation and inclusivity, allowing developers worldwide to contribute and extend the technology. This democratization of advanced video processing technology not only fosters global collaboration but also paves the way for further advancements in various fields reliant on reliable and secure video surveillance.

>> Read more about TISG trustable image sensor gateware

Topola — Topological (rubberband) router for printed circuit boards

Topola is an open-source topological (rubberband) router for printed circuit boards (PCBs). Unlike traditional maze routers, topological routers like Topola are not constrained by a grid or 45° angles, allowing for more efficient circuit board layouts (denser arrangement of components and traces, lower crosstalk, reflection, and electromagnetic interference). The goal of the project is to develop a dutifully maintained engine for interactive and automatic routing that can be used both as a standalone application and reusable software library integrated in popular open-source PCB electronic design automation (EDA) packages, giving designers a tool for developing high-quality open hardware designs without having to pay for expensive proprietary software.

>> Read more about Topola

TwPM — Open hardware implementation of Trusted Platform Module

The Trusted Platform Module or TPM is a dedicated hardware component designed for providing additional security features for computing platforms. Currently, the market is dominated by the TPMs based on chips from large silicon vendors. The common characteristic of these modules is the proprietary firmware implementation.

TwPM project aims to increase the trustworthiness of the TPM module (hence the TwPM), by providing the open-source firmware implementation for the TPM device, compliant to the TCG PC Client Specification.

The main goal of the project is an attempt to create open-source firmware stack, implementing the TCG PC Client Platform TPM Profile specification. Project aims to use already available open-source software components whenever possible (such as TPM simulators for TPM commands handling), while developing new code when necessary (such as LPC FPGA module, or low-level TPM FIFO interface handling). Another challenge is to overcome hardware restrictions and allow users to use the open-source TPM implementation on generally-accessible development boards.

>> Read more about TwPM

uberClock — High precision open hardware clocks using multi-mode crystal oscillators

Very precise clocks have many different use cases, but they are complex to make and expensive to buy - leaving high precision timing out of reach for many. Currently, there are no open hardware designs capable of delivering so called "Stratum 2" accuracy.

This project will design and build an open hardware clock exploiting the properties of multi-mode crystal oscillators using modern numerical methods for frequency stabilization. A Field-Programmable Gate Array (FPGA) will be used for digital signal processing functions, multiple Proportional-Integral-Derivative (PID) control loops, and executing all necessary calculations needed for dynamic, real-time frequency corrections. High-Level Synthesis (HLS) code will be developed using the CflexHDL+PipelineC toolset, in order to validate and further mature that emerging design flow for signal processing applications.

>> Read more about uberClock

UberDDR3 — Open Hardware DDR3 memory controller

UberDDR3 is set to transform the landscape of open-source technology as this will be above and beyond any previous opensourced DDR3 controller gatewares. This aims to unlock the full potential of DDR3 memory, aligning with the latest technological needs. We are dedicated to enhancing compatibility across diverse memory types and reaching higher speed. By integrating innovative features such as on-the-fly configuration, thermal management, ECC integration, and self-refresh mode, our goal is to elevate this open-source gateware to rival the performance of proprietary DDR3 controllers. This endeavor will empower the open-source community, ensuring that dependence on proprietary DDR3 controllers becomes a thing of the past, and setting a new benchmark for open-source hardware capabilities.

>> Read more about UberDDR3

uFork — A memory-safe pure-actor virtual machine

Applying the design principle of actors-all-the-way-down, uFork implements a virtual-machine that is memory-safe at the level of assembly-language instructions. All operations occur in the context of an actor message-event, which provides object-capability security throughout the system. The effects of individual instructions are isolated so they can only affect the state of their host actor until a transactional commit releases additional asynchronous message-events into the system. This isolation allows interleaved execution of multiple instruction streams, so multiple actors can make progress concurrently. The virtual-machine implements automatic memory management with garbage-collection, and fine-grained resource quotas are enforced by the processor.

>> Read more about uFork

uFork/FPGA — A memory-safe pure-actor processor soft-core

uFork is a novel microprocessor architecture based on dispatching immutable asynchronous message-events to reactive objects (actors) which manage private mutable state. Contention for shared mutable storage is eliminated, reducing complexity. Strong process and memory isolation prevents interference among tasks. Object-capability security (ocaps) provides fine-grained access control. The architecture has been validated by implementing a virtual-machine in software. This project will implement the design using FPGA hardware fully supported by open-source tooling.

>> Read more about uFork/FPGA

ULX4M — A modular open hardware FPGA platform

Embedded systems are everywhere, including in trusted environments. But what is really inside them? ULX3M is a modular version of the popular open hardware project ULX3S. ULX3M delivers a versatile programmable (FPGA) modular mainboard that can be used a wide choice of peripherals. The main board is "vendor neutral" and can be used with different FPGA vendors daughter boards. As the community continues to grow, lots of FPGA modules are written, and one goal of our boards would be that we can easily switch and check other vendor chips, and work more on vendor neutral code where possible. The project also improves SERDES availability. Some cheaper FPGA chips do not have lots of SERDES lines and when someone makes a board it needs to choose what peripheral will be using those SERDES lines. A daughter board that can be rotated in any position will allow more flexible usage. In that way, cheaper FPGA could be used to write all the code. With an open source design, users are not dependent on anyone to make boards and can run independent production.

>> Read more about ULX4M

Reverse Engineering Toolkit — Reducing e-waste through Reverse Engineering

According to the Global E-waste Statistics Partnership (GESP), electronic waste is estimated to increase to 74.4 Million Tonnes by 2030. A strong factor in the continuing increase of e-waste is the electronic industry artificially shortening the lifespan of their devices. Planned obsolescence, the inability to repair and abandoned software support all contribute to devices prematurely ending up in a waste stream. Older high-end consumer electronics devices have powerful components that, once open schematics, firmware and documentation has been created for them through reverse engineering, can be repurposed to create new and different devices.

To meet this aim, Unbinare is creating an open hardware reverse engineering toolkit consisting of the OI!STER (a tool for debugging and glitching MCUs), the UNBProbe (a passive, spring-loaded needle probe for probing PCBs), the UNBProbebase (a magnetic base with a prototyping area) and a breakout board - which allow to repurpose components salvaged from e.g. discarded mobile phones.

>> Read more about Reverse Engineering Toolkit

Verilog-A distiller — Automated porting of models from C to Verilog-A

Analog circuit simulators require compact device models in order to be able to simulate circuits. The de-facto standard language for compact device model dissemination is Verilog-A. Many legacy models exist that are coded for the SPICE3 circuit simulator in the C programming language. Manual conversion from C to Verilog-A is resource-intensive, time-consuming, and error-prone. This reduces the accessibility of legacy models and limits innovation. The Verilog-A Distiller project aims to automate conversion of SPICE3 device models from C to Verilog-A. By automating this conversion, we aim to streamline model implementation, reduce development time, and enhance compatibility across different simulators. Verilog-A Distiller is a converter written in Python that utilizes the pycparser library for reading the C code of SPICE3 models. The parsed models are pruned of unnecessary SPICE3-specific parts, upon which Verilog-A code is emitted. Projects like Ngspice put a lot of effort into cleaning up and improving legacy SPICE3 models. Verilog-A Distiller makes these models available across a wide range of simulators that support Verilog-A.

>> Read more about Verilog-A distiller

VexiiRiscv — Next generation of the VexRiscv in-order FPGA softcore

VexiiRiscv (Vex2Risc5) is a hardware project which aim at providing an free/open-source RISC-V in-order CPU which could scale from a simple microcontroller up to a multi-issue/debian capable cluster. While the project already surpasses VexRiscv in multiple domains (performances, 64 bits, debian), it still needs work and testing to reach feature parity (tightly coupled RAM, JTAG debug, optimization, ...), aswell to extend its scope (lightweight FPU, vector unit, ...). This grant would aim at filling those gaps aswell as improving its documentation.

>> Read more about VexiiRiscv

video box — Affordable open hardware video-to-network

The goal of the FOSDEM video box project is to develop a cheap, compact, open hardware & free software video-to-network solution. Initial motivation came from scratching our own itch: replacing 60 bulky, costly, not entirely free boxes currently used at the https://fosdem.org conference. Several other conferences have already used the current setup successfully. We expect this number to grow in the future. The solution being free software and open hardware should make it flexible to adapt to different environments, like education. Being cheap and compact encourages experimental use in areas difficult to foresee. On the hardware side, we use the open hardware Olimex Lime2 board (EU built!) as a base. We plan an open hardware hdmi input daughterboard, iterating on a simplified prototype that helped us verify feasibility. On the software side, the core Allwinner A20 chip has attracted a lot of free and open source development already. That enables us to focus our efforts on optimising video encoding on this platform from a hdmi signal to a compact network stream.

>> Read more about video box

LIP6 VLSI Tools — Logical validation of ASIC layouts

The software we run critically depends on the trustworthiness of the chips we use. LIP6's VLSI tools are one of the few user-operated toolchains for creating ASIC layouts where the full source code is available for inspection by anyone. This provides a significant contrast to commodity chips from vendors like Intel and AMD, where anything beyond coarse technical detail is shielded away by NDA's. This project will improve Coriolis2, HITAS/YAGLE and extend the whole toolchain so that it can perform Logical Validation. It will also upgrade the code to make it faster, able to handle larger ASIC designs, and add support for lower geometries (starting with 130nm) which are more energy-friendly.

>> Read more about LIP6 VLSI Tools

WireGuard on FPGA — FPGA implementation of Wireguard protocol written in SpinalHDL

This project will do an open hardware implementation of the WireGuard VPN protocol. The data plane with symmetric cryptography is implemented in HDL and should be able to handle 100 Gbit/s IP/Ethernet, whereas the asymmetric handshake is implemented on VexRiscv with accelerators and will be capable of maintaining thousands of concurrent connections. An off-the-shelf FPGA card handles the full protocol transparently: Ethernet/Ethernet or Ethernet/PCIe with one side ciphered and the other side plaintext.

>> Read more about WireGuard on FPGA

Wishbone Streaming — Add Streaming capabilities to Wishbone

On System-on-Chips (SoC) the commercial grade bus infrastructure is covered by patents and at best available "royalty-free" (but with no ability to change). A serious alternative with significant adoption is the Wishbone SoC Bus, which is an Open Standard but does not yet have a "streaming" capability. That capability is needed for high-throughput data paths and interfaces. This project will provide an enhancement to the current Wishbone SoC Bus specification, provide Reference Implementations and Bus Function Models (BFM) to easily allows unit tests for all Wishbone BFM users. For demonstration purposes the project will implement an example peripheral to prove the overall concept.

>> Read more about Wishbone Streaming

ZeroPhone Next — Hackable open hardware mobile phone

This project is building a hacker-friendly personal device platform, providing people with an assortment of building blocks that can be reused in building devices of their own. It sets out to deliver a featureful device for day-to-day use, with cellular and wireless connectivity, and bringing a powerful user interface that can easily be used in others' projects.

The platform's design prioritizes self-assembly capabilities, respect for the user's privacy, extensive documentation that makes the platform's building blocks all that more accessible, and forming a community aimed at helping other hackers build their own devices. The platform's inherent modularity also provides a testbench for designing open-source replacements for commonly closed-source parts of the DIY portable device ecosystem, as well as development of open firmware for currently-closed-source components.

>> Read more about ZeroPhone Next

ZSipOs — Open hardware for telephony encryption

ZSIPOs is a fully open source based encryption solution for internet telephony. It takes the shape of a little dedicated gadget you connect with a desktop phone. At its core the device does not have a normal chip capable of running regular software (including malware) but a so called FPGA (Field Programmable Gate Array). This means the device cannot be remotely updated (secure by design): the functionality is locked down into the chip, and the system is technically incapable of executing anything else. This means no risk of remote takeover by an attacker like with a normal computer or mobile phone connected to a network like the internet. The whole system is open hardware, and the full design is available for introspection. Normal users and security specialists get transparent access to the whole system and can easily check, what functionality is realized by the FPGA. This means anyone can verify the absence of both backdoors and bugs. ZSIPOs is designed to be fully compatible with the standard internet telephony system (SIP) which is the one used with traditional telephony numbers. The handling is done in principal by a regular internet phone (Dial, Confirm once – done). The cryptographic system is based on the standard RFC 6189 - ZRTP (with “Z” like Phil Zimmermann, the father of PGP), meaning it can also be used when using internet telephony on a laptop or mobile phone - of course without the additional guarantee of hardware isolation. There is no need to trust in an external service provider to establish the absolute privacy of speech communication. The exchange and verification of a secure key between the parties ensures end-to-end encryption, meaning that no third party can listen into the call. To that extent the device has a display to exchange security codes. The same approach can also also used for secure VPN Bridgeheads, secure storage devices and secure IoT applications and platforms. The ZSipOS approach is an appropriate answer on today security risks: it is completely decentralized, and has no dependency on central instances. It has a fully transparent design from encryption hardware to software. And it is easy to use with hundreds of millions of existing phones.

>> Read more about ZSipOs

ZSWatch — Open smartwatch including software, hardware, and mechanics

ZSWatch is a free and open source smartwatch you can build almost from scratch - including software, hardware, and mechanics. Everything from the lowest level BLE radio driver code to PCB and casing is available for introspection or to be customised to suit your needs.In this project, the team will add interesting new capabilities such as Heart Rate and Blood Oxygen sensor hardware, create a new iteration of hardware to improve wearability, improve documentation, make it easier to upgrade, and make various improvements to the software including optimising power consumption

>> Read more about ZSWatch