scalePNR
New place and route algorithms for large FPGAs
The scalePNR project focuses on enhancing digital circuit design for large Field-Programmable Gate Arrays (FPGAs), which are complex chips used in everything from consumer electronics to mobile phone base stations to cameras to AI accelerators to internet backbone infrastructure to advanced computing systems. Traditionally, designing these chips has been a highly specialized and time-consuming task, due to the complexity and computational demands of arranging and determining efficient wiring between the millions of tiny logic blocks they contain.
The goal of this effort is to tackle larger, more advanced FPGAs and make the process of designing circuits for these high-capacity chips more accessible and efficient, potentially leading to faster, more energy-efficient electronic devices. By researching and implementing new algorithms, the project aims to make it easier and quicker to design circuits that run cooler, faster, and more reliably, bringing the benefits of the latest technology to a broader audience and fostering innovation in numerous tech-driven sectors.
This project was funded through the NGI0 Entrust Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.
