Send in your ideas. Deadline December 1, 2024
Grant
Theme fund: NGI0 Discovery
Period: 2021-02 — 2022-10
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Hardware

Libre/OpenCores FuseSoc backend

Discovery and use of open hardware gateware through LibreCores and OpenCores

This project is archived. Due to circumstances, the project as planned did not take place. This page is left as a placeholder, for transparency reasons and to perhaps inspire others to take up this work.

Chip (FPGA/ASIC) development is normally done in a very hierarchical manner where gateware is used to build up subsystems which are combined to a full chip design. On paper, this leans very well for reusing parts in many different chip designs, but the actual amount of reuse has always been hampered by the lack of tooling to manage and combine gateware. Compare this to the software world where languages such as JavaScript, Python or Rust have a rich ecosystem of user-created reusable parts that can be used as a base to quickly build new applications. This project aims to provide a similar ecosystem for chip development where users can publish their cores, find the cores they need and build upon these to rapidly create new designs.

Why does this actually matter to end users?

Open collaboration (like for example on open source software) is based on the premise that together, we know more than we do alone. For open source software development, there is a long history of tools and infrastructure that you can easily setup and maintain for your project, so you can involve as many viewpoints and contributions as you can to make your program versatile, secure, user-friendly, creative, and so on. What's more, the community created around a project can keep software going long after an initial creator has left, updating and expanding it as needed.

For open source hardware, development is often more restricted, where businesses and researchers are forced to reinvent the wheel again and again. This does not only make bottom-up innovation unnecessarily expensive and uncompetitive, it also wastes precious resources. This project makes it easier for innovators to reuse chip designs and focus on how existing components can be combined to do exciting new things, speeding up innovation and research and development.

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This project was funded through the NGI0 Discovery Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 825322.