Verilog-A distiller
Automated porting of models from C to Verilog-A
Analog circuit simulators require compact device models in order to be able to simulate circuits. The de-facto standard language for compact device model dissemination is Verilog-A. Many legacy models exist that are coded for the SPICE3 circuit simulator in the C programming language. Manual conversion from C to Verilog-A is resource-intensive, time-consuming, and error-prone. This reduces the accessibility of legacy models and limits innovation. The Verilog-A Distiller project aims to automate conversion of SPICE3 device models from C to Verilog-A. By automating this conversion, we aim to streamline model implementation, reduce development time, and enhance compatibility across different simulators. Verilog-A Distiller is a converter written in Python that utilizes the pycparser library for reading the C code of SPICE3 models. The parsed models are pruned of unnecessary SPICE3-specific parts, upon which Verilog-A code is emitted. Projects like Ngspice put a lot of effort into cleaning up and improving legacy SPICE3 models. Verilog-A Distiller makes these models available across a wide range of simulators that support Verilog-A.
Run by University of Ljubljana, Faculty of Electrical Engineering
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
