FastWave

Whilst the fields of open-source hardware design tooling (including synthesizers and layout tools, and open-source digital logic/VLSI gateware) have recently experienced a significant renaissance, simulation visualization tools have not enjoyed similar advancements. This is noteworthy given that verification comprises approximately 80% of the digital logic development cycle. Efficient visualization and debugging of SOC simulations are thus becoming ever more critical.

Fastwave, currently developed as a VCD (Value Change Dump) parser in Rust, along with its visualization frontend, Surfer, aims to address this gap. Future iterations of Fastwave will enable advanced visualization of simulation states through custom user plugins. Potential applications include, but are not limited to, visualizing CPU pipeline states with pipeline diagrams or representing mesh network activity by simply loading a VCD file. Plans for expanding the Fastwave suite include features like tracing signals to their source, allowing users to pinpoint the HDL conditions that prompted changes in simulation signal states. Ultimately, Fastwave intends to reduce the workload for digital logic designers by enabling them to align the tool's visual outputs with the mental models they already have of their hardware systems.