EDA

What is Electronic Design Automation?

Electronic Design Automation or EDA is a category of software and hardware tools used by engineers to design electronic systems like Integrated Circuits (ICs) and Printed Circuit Boards (PCBs). Because EDA tools automate complex tasks in design, simulation, testing, and manufacturing processes, they're an indispensable part of the development of electronic systems.

Information sources

Read the article Changing the Chip Industry: How Public Investment Has Grown Open Silicon published in Linux Magazine written by Jeffrey A. McGuire to get an indepth overview of the current state of Open EDA and how it contributes to digital autonomy.

Listen to the NGI Zero podcast episode Democratizing Chip Design. Christophe Alexandre goes deep into the topic of open EDA and explains how it can contribute to a more resilient and accessible chip ecosystem. Christophe is co-founder of keplertech.io, a company pioneering the next generation of EDA technologies and co-authored Naja, a project supported by NLnet.

The 15-minute talk Open-source Silicon Chips by Luca Alloatti provides a quick overview of the problems with closed-source chip design, the progress being made with free and open source EDA tools, next steps and the opportunities for users, society and companies. Luca is is the president of the Free Silicon Foundation which promotes the freedom of silicon integrated circuits and is an NGI0 partner.

EDA projects supported by NLnet

Chips4Makers ASICs —

Current scaling of micro-electronics is focused on improving power, performance and cost per device but with an exponentially increasing start-up cost related to the increased process complexity. For the design of custom chips currently expensive proprietary electronic design automation (EDA) tools need to be used and hefty license fees are due for blocks implementing specific functions like the CPU, USB etc. All this together makes custom chip development only accessible for high-volume production and proprietary designs. In this project a development version of the libre licensed Libre-SOC system-on-a-chip will be manufactured in a 0.18um process combined with development on the open source tools and open source chip building blocks to make this possible. Development on the free and open source tools will be focused on making them compatible with the selected process and the building block development will be focused on the so-called standard cell library, the IO library and the SRAM compiler. This project fits in the longer term goal of the Chips4Makers project to make low-volume custom chip production possible using mature process technologies and free and open source tool chains and building blocks. Purpose is to get innovation using custom chips within reach of small start-ups, makers and even hobbyists.

Read more about Chips4Makers ASICs.

Edalize ASIC backend — Create open hardware silicon with a fully free software toolchain

Affordable Open Source ASIC development and custom silicon has been a long-standing goal in the community. This will unlock innovation that has previously only been possible for the largest tech companies, allowing for the creation of deployable, trusted Open Source based hardware.

Step by step, this goal has come closer in the last few years as individuals, companies and academic institutions have filled in the missing pieces. Today we have a fully open source end-to-end flow for building open source ASIC - but the effort of on-boarding existing designs remains high. This project aims to provide an easy way to onboard existing gateware and full designs to an open source ASIC flow by creating a FuseSoC backend that targets this toolchain. This will enable a smoother transition from projects already running on FPGAs to also be targeting ASIC flows. It will also allow easier switching between different open source ASIC flows at the point when there are several alternatives to choose from.

In addition to the backend itself, a reference design containing SERV, the world’s smallest RISC-V CPU, will be run through the flow and committed to actual silicon. This will provide a way to guarantee a working flow and provide a simple but usable reference for everyone else looking to onboard their designs. Enabling and demonstrating this path will allow a fully trustworthy path for the fabrication of system-on-a-chip ICs, with no proprietary or closed tools as part of the flow and hence completely inspectable at all stages. This paves the road for other more complex FuseSoC-based open source silicon projects such as OpenTitan and SweRVolf.

Read more about Edalize ASIC backend.

KiCad — Professional open source electronics design application

KiCad is a free and open source electronics design application (EDA) that can handle everything from the most basic schematic to a complex hierarchical design with hundreds of sheets. It allows electronics designers to use a toolchain that itself is technically transparent, and that can be customised when needed. KiCad has already been successfully used for key open hardware projects such as the LibreRouter, the HackRF, MNT Reform and UPSAT. This project will contribute to furthering the mission of providing professional level tools for users who design electronics for a living.

Read more about KiCad, KiCad-10, KiCad-IPC.

LibrEDA — An integrated development environment for chip design

Because digital circuits are a core part of today’s society there is a significant value in free and open chips and, equally important, free and open design software that is accessible also to small entities. Not only would this enhance trust through transparency and digital sovereignty through distributed knowledge but it would also be a fertile ground for education, hobbyists and small enterprises. The main goal of this project is to create a new libre-software framework for the physical design of digital integrated circuits. The framework is meant to simplify the development of chip layout tools, i.e. the tools used to convert a gate-level netlist into a fabrication-ready layout. This includes fundamental data structures and algorithms, interface definitions of the design algorithms (e.g. placement, routing or timing analysis), input/output libraries for commonly used file formats as well as documentation and example implementations. Two variants will be pursued in parallel: One with a clear focus on simplicity and education and another with a focus on performance and scalability. Another part of the project is the continuation of the ‘LibreCell’ standard-cell generator and characterization tool.

Read more about LibrEDA.

LibrePCB — EDA software suite to develop printed circuit boards

LibrePCB is a free and open source electronics design automation (EDA) software suite to develop printed circuit boards (PCBs). It runs on all major platforms and aims to be easy to use, while still beeing able to create professional schematics and PCBs. The goal is to make creating electronics easier, more efficient and less error-prone by using modern technologies and user interface concepts. LibrePCB therefore streamlines the whole PCB design process — from installing part libraries to ordering the final PCB design. Having such a free, powerful EDA software is the basement for the whole open hardware community as it allows us to reduce the dependency to proprietary and expensive technologies and empowers everyone to develop hardware for free, from hobbyists to professionals.

Read more about LibrePCB, LibrePCB 2.0.

Mosaic — Trustworthy open hardware design tool for electrical engineers

Today, the chip design industry is deeply proprietary with NDAs at every level, which means it is not possible to share design files at all, which in turn stifles innovation and transparency in chip design. In order to create a chip design industry that can be trusted with our digital lives, and is accessible to educational institutions and small business, it is essential to develop powerful open source tools for chip design, which can be used by anyone and allows unhindered collaboration. Mosaic is a tool that attacks the first design phase of an analog chip, or analog peripherals for a digital one: design and simulation of the schematic. It will also interact with other phases of the design as needed. Unlike existing open source solutions it will be catered towards chip design, based on modern technologies, and extensive UX design.

Read more about Mosaic.

Mosaic Simulation — EDA tool for analog chip design

Today, the chip design industry is deeply proprietary with NDAs at every level, which means it is not possible to share design files at all. This in turn stifles learning, innovation and transparency in chip design. In order to create a chip design industry that can be trusted with our digital lives, and which is accessible to educational institutions and small business, it is essential to develop powerful open source tools for chip design. Anyone should be able to use these tools, allowing for unhindered collaboration.

Mosaic is a tool that attacks the first design phase of an analog chip, or analog peripherals for a digital one: design and simulation of the schematic. In this follow-up grant the team will focus on simplification, distribution, and polish - making Mosaic easier to install and use as well as maintain.

Read more about Mosaic Simulation.

Naja — EDA tool focused on post logic synthesis

Naja is an EDA (Electronic Design Automation) project aiming at offering open source data structures and APIs for the development of post logic synthesis EDA algorithms such as: netlist simplification (constant and dead logic propagation), logic replication, netlist partitioning, ASIC and FPGA place and route, …

In most EDA flows, data exchange is done by using standard netlist formats (Verilog, LEF/DEF, EDIF, …) which were not designed to represent data structures content with high fidelity. To address this problem, Naja relies on Cap'n Proto open source interchange format.

Naja also emphasizes EDA applications parallelization (targeting in particular cloud computing) by providing a robust object identification mechanism allowing to partition and merge data across the network.

Read more about Naja, Naja DNL, Timing Modeling and Integrated Verification in Naja.

pcb-rnd — Modular printed circuit board editor

Pcb-rnd is a modular printed circuit board editor that is designed with the UNIX mind set. It has a convenient GUI for editing the graphical data of the board but is also has a handy command line interface. Both the GUI and the CLI aspects are scriptable (in more than 10 scripting languages) and pcb-rnd can also process boards as a headless converter tool. It has support for various proprietary schematics/netlist and board formats which makes it also a good choice for converting free hardware designs coming in proprietary formats to free file formats. Among the upcoming challenges are a full rewrite of the Design Rule Checker, more file format support and making the menu system even more dynamic to match the modular nature of pcb-rnd better.

Read more about pcb-rnd.

pcb-rnd, sch-rnd — Open source EDA suite

Ringdove EDA is a modular, portable Electronics Design Automation toolkit mainly targeting the Printed Circuit Board design workflow. The two flagship projects in Ringdove are sch-rnd (schematics capture) and pcb-rnd (printed circuit board editing). Because of the modular layout of the code and the active management of dependencies, both projects are highly portable, both in time (old, present and future systems) and in workflows (interactive graphical design or interactive command line usage or headless automated processing). Ringdove also strives to support file formats of other EDA software, especially for loading proprietary formats, making existing/legacy hardware designs more accessible to the Open Source community.

Read more about pcb-rnd, sch-rnd, pcb-rnd + sch-rnd alien formats.

Slintify LibrePCB 2.0 — Add missing features to Slint UI toolkit to accommodate demanding applications

The project summary for this project is not yet available. Please come back soon!

Read more about Slintify LibrePCB 2.0.

Topola — Topological (rubberband) router for printed circuit boards

Topola is an open-source topological (rubberband) router for printed circuit boards (PCBs). Unlike traditional maze routers, topological routers like Topola are not constrained by a grid or 45° angles, allowing for more efficient circuit board layouts (denser arrangement of components and traces, lower crosstalk, reflection, and electromagnetic interference). The goal of the project is to develop a dutifully maintained engine for interactive and automatic routing that can be used both as a standalone application and reusable software library integrated in popular open-source PCB electronic design automation (EDA) packages, giving designers a tool for developing high-quality open hardware designs without having to pay for expensive proprietary software.

Read more about Topola, Automatic component and via placement for Topola.

Analog/Mixed-Signal Library — OSHW component library for ASIC design

One of the gaps in the open chip toolchain is a libre-licensed analog/mixed-signal library. Having access to such a library contributes to having a fully open ASIC design infrastructure through which secure and trustworthy open hardware can subsequently be built.

This project is trying to fill that void. The first part of the project consists of enhancing and stabilising the underlying PDKMaster project, and allow it to facilitate programmatic co-generation of circuit and layout with integrated support for circuit simulation. This should make resulting circuits DRC and LVS clean by design. Second part of the bootstrapping effort is then to implement a set of scalable analog/mixed-signal blocks which can be integrated into PDKMaster. The initial set will consist of the following 4 core blocks: a voltage reference, a PLL (phase-locked loop), a low frequency, low accuracy ADC and a low frequency, low accuracy DAC.

The overall focus is on proving the overall suitability of the PDKMaster framework, rather than on the complexity and difficulty of the individual analog/mixed-signal blocks which are to be added. Thanks to proper documentation and examples, users can start expanding the available building blocks by adding their own contributions.

Read more about Analog/Mixed-Signal Library.

Frugal EDA — Energy-efficient circuits and systems through quantum superconductivity

FRUGAL EDA is an open-source user-friendly software design suite dedicated to energy-frugal electronics based on the amazing quantum physical properties of superconductivity. Its objective is to enable the design of energy-efficient ultra-high-speed (up to clock frequencies of several hundreds GHz) quantum-based circuits and systems for the widest possible audience. FRUGAL will emulate the development of new circuits and functionalities so that disruptive quantum electronics can take its place in the current highly-competitive emerging technology landscape. One goal is to increase the number of students and newcomers interested to design quantum-based circuits without the need of unaffordable tools, proprietary technologies or steep learning curves. FRUGAL embeds a set of open-source software tools comprising a schematic editor(LibrePCB), a SPICE netlist converter (L2SPICE), quantum time-domain simulators (JSIM and JoSIM) and a layout editor (KLayout). More designer-oriented features will be added along the course of development.

Read more about Frugal EDA.

IC workspace — Open Source IC Design Management Tool

IC workspace is a design management tool that addresses the complexity of working with scattered design domains that span analog, digital, EDA tools, flows and process development kits (PDKs). In the process of designing a chip, multiple people need an common organized structure to work on design capturing schematics, generator, custom layout, high level digital design combined with test benches in various domain specific formats. Each tool in the open source domain has it own file structure. IC workspace is an open source framework with tools that individual designers and teams use to organize design files in a local workspace. IC workspace integrates interface to source code version control systems, the various tools in the design flow and organizes the files in a workspace with an unified component structure with dependency attributes. IC workspace sets common language and methodologies for both analog and digital – frontend/backend designer to maximize productivity within the open source chip design ecosystem of tools, PDK’s and people.

Read more about IC workspace.

KiCad Frontpanel Generator — Create matching front panels for KiCad PCBs automatically

The most popular free and open source design suite for Printed Circuit Boards (PCBs) likely is KiCad. When designing a PCB with buttons and switches, that's meant to be operated by an end user, the PCB usually is covered by a front panel. The front panel has cut-outs and labels for switches, displays and indicator lights. Designing a suitable front panel often is a time-consuming extra step, because all the cut-outs and labels must be placed manually at precise locations to match the PCB components. KiCad Frontpanel Generator creates matching front panels for KiCad PCBs automatically. The PCB designer defines cut-outs and labels in unused layers of footprints and in the PCB. The Front Panel Generator then uses the shapes from these layers to generate a suitable cover plate.

Read more about KiCad Frontpanel Generator.

openXC7 — Improve hardware support for open source FPGA tooling

FPGAs are reconfigurable chips capable of handling many electronic signals in parallel. They are used in network equipment like backbone switches, firewalls, video devices like surveillance cameras and radio equipment like mobile-phone base stations, radar systems and satellites to process high volumes of data with very low latency. FPGAs are also used to test digital circuit designs before they are manufactured as chips.

The functionality of FPGAs is determined by a configuration file which is loaded into the FPGA at power-on. The configuration file is usually generated from a design file by a proprietary tool provided by the manufacturer of the FPGA.

openXC7 will provide a complete set of open source tools to generate a configuration file for the widely used family of Xilinx Series 7 FPGAs from manufacturer Xilinx/AMD without having to use any proprietary tools. This will empower digital design engineers to have the guarantee that no backdoor is implemented on FPGA based devices by the proprietary design tool provided by the vendor.

The availability of the source code of the FPGA design tool will also allow anyone to come up with new use cases for FPGAs currently not possible with existing tools.

In this project the team will implement gigabit transceiver support, both for the widely used Artix7 and the Kintex7 families of devices, thus enabling complete open source network infrastructure (e.g. an open source 10 GB Ethernet switch). The second focal point will be identifying and fixing issues that arise from the community of users of the toolchain.

Read more about openXC7.

QUAntum bits of This and That (QUATT) — Design and understand solid-state quantum circuits

QUAntum bits of This and That (QUATT) has the objective of providing visual outreach tools to design and understand solid-state quantum circuits based on the FrugalEDA software design suite for superconductors. QUATT fills the gap between the quantum properties of superconducting devices obtained by simulations, including quantum interferences and qubits states and intrication, and innovative visual representations that capture the essence of the physics of such systems and help the end-user to design quantum circuits more intuitively.

Read more about QUAntum bits of This and That (QUATT).

TISG trustable image sensor gateware — FPGA based camera providing encrypted video streams

The TISG project is set to develop a groundbreaking open-source, FPGA-based camera system, focusing on the implementation of the MIPI-CSI2 standard for connecting a wide range of image sensors to FPGAs. The development process involves leveraging open-source FPGA tools and formal verification methods to ensure robust security and functionality. The primary purpose is to create a secure, versatile, and accessible video processing platform that addresses current security vulnerabilities in video-based systems. By eliminating reliance on proprietary software and enabling formal hardware verification, the project aims to significantly reduce the risk of backdoors and cyber threats. The general public will benefit from enhanced security in areas like home surveillance, public safety, and infrastructure monitoring. Additionally, the open-source nature of the project promotes innovation and inclusivity, allowing developers worldwide to contribute and extend the technology. This democratization of advanced video processing technology not only fosters global collaboration but also paves the way for further advancements in various fields reliant on reliable and secure video technology.

Read more about TISG trustable image sensor gateware.

VeriBench — Verilog-AMS Testbench Framework for Open EDA Verification

Verilog-AMS is a hardware description language developed to standardise the description of device models and circuits in analog and mixed-signal design. It is widely used across both proprietary and open-source Electronic Design Automation (EDA) toolchains. While Verilog-AMS standardises hardware descriptions, the behaviour and numerical accuracy of simulators and model compilers remain tool-dependent and require systematic verification. VeriBench will provide automated Verilog-AMS testbenches that enable systematic verification of semiconductor device models and representative analog and logic circuits. The testbenches will support realistic simulation contexts using open Process Design Kits (PDKs). They will enable cross-validation, regression testing, and benchmarking across open-source simulators such as Gnucap and ngspice, as well as Verilog-A/AMS model compilers, including OpenVAF and Gnucap’s modelgen-verilog. By providing documented benchmarks, reference results, and ready-to-run examples, VeriBench will validate open-source simulation toolchains, build trust in their results, improve reproducibility, and lower the barrier to entry for users and contributors.

Read more about VeriBench.