EDA

Analog/Mixed-Signal Library — OSHW component library for ASIC design

One of the gaps in the open chip toolchain is a libre-licensed analog/mixed-signal library. Having access to such a library contributes to having a fully open ASIC design infrastructure through which secure and trustworthy open hardware can subsequently be built.

This project is trying to fill that void. The first part of the project consists of enhancing and stabilising the underlying PDKMaster project, and allow it to facilitate programmatic co-generation of circuit and layout with integrated support for circuit simulation. This should make resulting circuits DRC and LVS clean by design. Second part of the bootstrapping effort is then to implement a set of scalable analog/mixed-signal blocks which can be integrated into PDKMaster. The initial set will consist of the following 4 core blocks: a voltage reference, a PLL (phase-locked loop), a low frequency, low accuracy ADC and a low frequency, low accuracy DAC.

The overall focus is on proving the overall suitability of the PDKMaster framework, rather than on the complexity and difficulty of the individual analog/mixed-signal blocks which are to be added. Thanks to proper documentation and examples, users can start expanding the available building blocks by adding their own contributions.

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Chips4Makers ASICs —

Current scaling of micro-electronics is focused on improving power, performance and cost per device but with an exponentially increasing start-up cost related to the increased process complexity. For the design of custom chips currently expensive proprietary electronic design automation (EDA) tools need to be used and hefty license fees are due for blocks implementing specific functions like the CPU, USB etc. All this together makes custom chip development only accessible for high-volume production and proprietary designs. In this project a development version of the libre licensed Libre-SOC system-on-a-chip will be manufactured in a 0.18um process combined with development on the open source tools and open source chip building blocks to make this possible. Development on the free and open source tools will be focused on making them compatible with the selected process and the building block development will be focused on the so-called standard cell library, the IO library and the SRAM compiler. This project fits in the longer term goal of the Chips4Makers project to make low-volume custom chip production possible using mature process technologies and free and open source tool chains and building blocks. Purpose is to get innovation using custom chips within reach of small start-ups, makers and even hobbyists.

>> Read more about Chips4Makers ASICs

IC workspace — Open Source IC Design Management Tool

IC workspace is a design management tool that addresses the complexity of working with scattered design domains that span analog, digital, EDA tools, flows and process development kits (PDKs). In the process of designing a chip, multiple people need an common organized structure to work on design capturing schematics, generator, custom layout, high level digital design combined with test benches in various domain specific formats. Each tool in the open source domain has it own file structure. IC workspace is an open source framework with tools that individual designers and teams use to organize design files in a local workspace. IC workspace integrates interface to source code version control systems, the various tools in the design flow and organizes the files in a workspace with an unified component structure with dependency attributes. IC workspace sets common language and methodologies for both analog and digital – frontend/backend designer to maximize productivity within the open source chip design ecosystem of tools, PDK’s and people.

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KiCad — Professional open source electronics design application

KiCad is a free and open source electronics design application (EDA) that can handle everything from the most basic schematic to a complex hierarchical design with hundreds of sheets. It allows electronics designers to use a toolchain that itself is technically transparent, and that can be customised when needed. KiCad has already been successfully used for key open hardware projects such as the LibreRouter, the HackRF, MNT Reform and UPSAT. This project will contribute to furthering the mission of providing professional level tools for users who design electronics for a living.

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KiCad-10 — Cross Platform Electronics Design Automation Suite

KiCad is a free and open source electronics design application (EDA) that can handle everything from the most basic schematic to a complex hierarchical design with hundreds of sheets. It allows electronics designers to use a tool chain that itself is technically transparent, and that can be customized when needed. KiCad has already been successfully used for key open hardware projects such as the LibreRouter, the HackRF, MNT Reform and UPSAT. This project will improve KiCad's IPC API and editing capabilities, and pursue upgrades for schematics and symbols handling, PCB design, library tooling, and documentation.

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LibrePCB 2.0 — New UI & powerful features for a future-proof LibrePCB

LibrePCB is a free and open source electronics design automation (EDA) software suite to develop printed circuit boards (PCBs). It runs on all major platforms and aims to be easy to use, while still beeing able to create professional schematics and PCBs. While it is already used productively by people all around the world, the development of new features became to stuck because of limitations of the current UI concept. To pave the way for new features, a completely new UI will be developed with the goal of having a unified, tabbed window as known and proven by many other applications. In addition, a first attempt of moving from C++ to the safer language Rust will help us to benefit from modern technologies. Together with more import/export capabilities, performance improvements and other frequently requested features the outcome will be released to users by a new major version LibrePCB 2.0.

>> Read more about LibrePCB 2.0

Naja — EDA tool focused on post logic synthesis

Naja is an EDA (Electronic Design Automation) project aiming at offering open source data structures and APIs for the development of post logic synthesis EDA algorithms such as: netlist simplification (constant and dead logic propagation), logic replication, netlist partitioning, ASIC and FPGA place and route, …

In most EDA flows, data exchange is done by using standard netlist formats (Verilog, LEF/DEF, EDIF, …) which were not designed to represent data structures content with high fidelity. To address this problem, Naja relies on Cap'n Proto open source interchange format.

Naja also emphasizes EDA applications parallelization (targeting in particular cloud computing) by providing a robust object identification mechanism allowing to partition and merge data across the network.

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Naja DNL — Add Dissolved and Batch Netlists to Naja EDA

Naja is an EDA (Electronic Design Automation) project aiming at offering open source data structures and APIs for the development of post logic synthesis EDA algorithms such as: netlist simplification (constant and dead logic propagation), logic replication, netlist partitioning, ASIC and FPGA place and route, … In most EDA flows, data exchange is done by using standard netlist formats (Verilog, LEF/DEF, EDIF, …) which were not designed to represent data structures content with high fidelity.

To overcome this problem, Naja relies on Cap'n Proto open source interchange format. Naja also emphasizes EDA applications parallelization (targeting in particular cloud computing) by providing a robust object identification mechanism allowing to partition and merge data across the network.

The core of Naja is formed by two interrelated data structures: the Structured Netlist (SNL) and the Dissolved Netlist (DNL). SNL is tailored for high-fidelity representation of hierarchical netlists, while DNL offers a flattened netlist view, optimized for rapid, multi-threaded analysis and optimization tool development.

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Timing Modeling and Integrated Verification in Naja — Timing aware netlist optimisation with Logic Equivalence Checking

Naja is an open-source Electronic Design Automation (EDA) project focused on the editing, optimization, and verification of post-synthesis netlists—data structures that describe the logical connectivity of electronic circuits after synthesis.

This project will introduce two key components to Naja and the broader open hardware and EDA ecosystems: a flexible high-performance timing model engine designed for tight integration with placement and routing algorithms, and a built-in logic equivalence checking (LEC) infrastructure, optimized for incremental verification of netlist modifications—particularly in the context of Engineering Change Orders (ECOs). By addressing these important gaps in timing-aware design and incremental formal verification, the project aims to contribute important technological bricks to the open-source community, supporting the development of more capable and reliable open source EDA tools.

>> Read more about Timing Modeling and Integrated Verification in Naja

pcb-rnd + sch-rnd alien formats — Importers for proprietary file formats in Ringdove EDA

Ringdove EDA is a modular, portable Electronics Design Automation toolkit (primarily for Printed Circuit Board design) with a distinctive focus on the UNIX philosophy. The two flagship subprojects are sch-rnd (schematics capture) and pcb-rnd (printed circuit board editing). Because of the modular code and reduced dependencies, both projects are highly portable, both in time (old, present and future systems) and in workflows (interactive GUI, interactive CLI or headless automated processing). Ringdove also strives to support file formats of other EDA software, especially for loading proprietary formats, making existing/legacy hardware designs more accessible to the Open Source community.

>> Read more about pcb-rnd + sch-rnd alien formats

Slintify LibrePCB 2.0 — Add missing features to Slint UI toolkit to accommodate demanding applications

The project summary for this project is not yet available. Please come back soon!

>> Read more about Slintify LibrePCB 2.0

Topola — Topological (rubberband) router for printed circuit boards

Topola is an open-source topological (rubberband) router for printed circuit boards (PCBs). Unlike traditional maze routers, topological routers like Topola are not constrained by a grid or 45° angles, allowing for more efficient circuit board layouts (denser arrangement of components and traces, lower crosstalk, reflection, and electromagnetic interference). The goal of the project is to develop a dutifully maintained engine for interactive and automatic routing that can be used both as a standalone application and reusable software library integrated in popular open-source PCB electronic design automation (EDA) packages, giving designers a tool for developing high-quality open hardware designs without having to pay for expensive proprietary software.

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Automatic component and via placement for Topola — Complete PCB schematic-to-layout flow

The first step in designing a printed circuit board (PCB) layout is choosing where to place the components. This task is tedious and time-consuming, often requiring just as much effort as the process of routing the traces that comes afterwards. Fortunately, component placement can be automated with software called an autoplacer, just as routing traces can be automated with a program known as an autorouter. The goal of this project is to develop a component autoplacer for the PCB autorouting system Topola, turning it into a complete PCB schematic-to-layout flow. To find the best locations for components, the autoplacer will use a probabilistic optimization algorithm known as simulated annealing.

>> Read more about Automatic component and via placement for Topola

VeriBench — Verilog-AMS Testbench Framework for Open EDA Verification

Verilog-AMS is a hardware description language developed to standardise the description of device models and circuits in analog and mixed-signal design. It is widely used across both proprietary and open-source Electronic Design Automation (EDA) toolchains. While Verilog-AMS standardises hardware descriptions, the behaviour and numerical accuracy of simulators and model compilers remain tool-dependent and require systematic verification. VeriBench will provide automated Verilog-AMS testbenches that enable systematic verification of semiconductor device models and representative analog and logic circuits. The testbenches will support realistic simulation contexts using open Process Design Kits (PDKs). They will enable cross-validation, regression testing, and benchmarking across open-source simulators such as Gnucap and ngspice, as well as Verilog-A/AMS model compilers, including OpenVAF and Gnucap’s modelgen-verilog. By providing documented benchmarks, reference results, and ready-to-run examples, VeriBench will validate open-source simulation toolchains, build trust in their results, improve reproducibility, and lower the barrier to entry for users and contributors.

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pcb-rnd — Modular printed circuit board editor

Pcb-rnd is a modular printed circuit board editor that is designed with the UNIX mind set. It has a convenient GUI for editing the graphical data of the board but is also has a handy command line interface. Both the GUI and the CLI aspects are scriptable (in more than 10 scripting languages) and pcb-rnd can also process boards as a headless converter tool. It has support for various proprietary schematics/netlist and board formats which makes it also a good choice for converting free hardware designs coming in proprietary formats to free file formats. Among the upcoming challenges are a full rewrite of the Design Rule Checker, more file format support and making the menu system even more dynamic to match the modular nature of pcb-rnd better.

>> Read more about pcb-rnd