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Physical Chip Design Framework
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Physical Chip Design Framework

[Physical Chip Design Framework]

Because digital circuits are a core part of today’s society there is a significant value in free and open chips and, equally important, free and open design software that is accessible also to small entities. Not only would this enhance trust through transparency and digital sovereignty through distributed knowledge but it would also be a fertile ground for education, hobbyists and small enterprises. The main goal of this project is to create a new libre-software framework for the physical design of digital integrated circuits. The framework is meant to simplify the development of chip layout tools, i.e. the tools used to convert a gate-level netlist into a fabrication-ready layout. This includes fundamental data structures and algorithms, interface definitions of the design algorithms (e.g. placement, routing or timing analysis), input/output libraries for commonly used file formats as well as documentation and example implementations. Two variants will be pursued in parallel: One with a clear focus on simplicity and education and another with a focus on performance and scalability. Another part of the project is the continuation of the ‘LibreCell’ standard-cell generator and characterization tool.

Why does this actually matter to end users?

Consumers and businesses overpay for computer hardware, because the market is not working well. When you go to a store to buy a laptop or mobile phone, you may see different brands on the outside but choice in terms of what is inside the box (in particular the most expensive component, the processor technology) is pretty much limited to the same core technologies and large vendors that have been in the market for decades. This has a much bigger effect on the users than just the hefty price tag of the hardware, because the technologies at that level impact all other technologies and insecurity at that level break security across the board.

In the field of software, open source has already become the default option in the market for any new setup. In hardware, the situation is different. Users - even very big users such as governments - have very little control over the actual hardware security of the technology they critically depend on every day. Security experts continue to uncover major security issues, and users are rightly concerned about the security of their private data as well as the continuity of their operations. But in a locked-down market there is little anyone can do, because the lack of alternatives. European companies are locked out of the possibility to contribute solutions and start new businesses that can change the status quo.

To make open hardware design accessible, this project will simplify the development of chip layout tools. These tools are needed to turn a description of how components in a circuit will work, to an computer chip layout to be produced. This way the project can both help to educate students and hobbyists about chip design as well as provide small enterprises and organizations with publicly available tooling to create their own open hardware.

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This project was funded through the NGI0 PET Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 825310.