SWD Debug support in VexRiscv
Functional SWD debugging support for VexRiscv/VexiiRiscv
The VexRiscv-Debug project aims to extend the popular open-source VexRiscv RISC-V soft CPU core with functional debugging support enabling essential development and bring-up capabilities for developers building debuggable RISC-V SoCs on custom ASIC or FPGA platforms. This includes making Vexriscv fully Riscv Debug specification compliant and additionally adding support for Serial Wire Debug (SWD), which is a widely used industry specification set forth by ARM.
- The project's own website: https://saketsinha.de/VexRiscv-Debug
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
