VeriBench

Verilog-AMS is a hardware description language developed to standardise the description of device models and circuits in analog and mixed-signal design. It is widely used across both proprietary and open-source Electronic Design Automation (EDA) toolchains. While Verilog-AMS standardises hardware descriptions, the behaviour and numerical accuracy of simulators and model compilers remain tool-dependent and require systematic verification. VeriBench will provide automated Verilog-AMS testbenches that enable systematic verification of semiconductor device models and representative analog and logic circuits. The testbenches will support realistic simulation contexts using open Process Design Kits (PDKs). They will enable cross-validation, regression testing, and benchmarking across open-source simulators such as Gnucap and ngspice, as well as Verilog-A/AMS model compilers, including OpenVAF and Gnucap’s modelgen-verilog. By providing documented benchmarks, reference results, and ready-to-run examples, VeriBench will validate open-source simulation toolchains, build trust in their results, improve reproducibility, and lower the barrier to entry for users and contributors.