Automatic component and via placement for Topola
Complete PCB schematic-to-layout flow
The first step in designing a printed circuit board (PCB) layout is choosing where to place the components. This task is tedious and time-consuming, often requiring just as much effort as the process of routing the traces that comes afterwards. Fortunately, component placement can be automated with software called an autoplacer, just as routing traces can be automated with a program known as an autorouter. The goal of this project is to develop a component autoplacer for the PCB autorouting system Topola, turning it into a complete PCB schematic-to-layout flow. To find the best locations for components, the autoplacer will use a probabilistic optimization algorithm known as simulated annealing.
- The project's own website: https://topola.dev
Run by Topola
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
