RIVET
Cointegration of RISC-V systems with Ethernet
The goal of the RIVET project is to develop and incorporate an Ethernet Media Access Controller (MAC) into an already existing organized open-source framework for agile development of RISC-V Systems-on-Chip (SoC) such as Chipyard. This work enables development engineers and researchers to equip their custom compute ASIC and FPGA prototypes with a "plug-and-play" Internet access feature while providing a ready testbed for next-generation networking devices. By upstreaming the results to Chipyard, the project will deliver the first fully parameterizable Chisel-based Gigabit Ethernet MAC design generator solution in that ecosystem, dramatically lowering the barrier for the global open-hardware and VLSI communities to build network-capable RISC-V systems and subsequently integrate them on a chip.
Run by Department of EECS, Faculty of Engineering, University of Kragujevac
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
