PyUVM SPI Verification Component
Add Serial Peripheral Interface support to PyUVM verification tool
In recent years, many open source projects have emerged making chip design and verification possible without the need for the common proprietary SystemVerilog tools. The emergence of PyUVM brought the power of the Universal Verification Methodology (UVM) to the Python ecosystem. To strengthen this ecosystem, reliable and re-usable verification components are key factors to shift left and focus verification effort on functional bugs of complex designs. The PyUVM SPI verification component is a configurable agent designed for SPI protocol based on PyUVM. Tutorials, documentation and test bench examples will be available to promote its usage and ensure that the ability to deliver high-confidence, verified silicon is no longer a privilege of well-funded corporations, but a standard accessible to the entire open-source community.
- The project's own website: https://github.com/calonso88/pyuvm-spi
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
