openCologne/PCIe
Create PCIe EndPoint for GateMate FPGA's
This project is about creating open source PCIE EndPoint gateware, without requiring vendor locked components. It will be delivered as a well-structured, easy to follow, unencrypted System Verilog RTL; free to use, inspect and modify, and portable to other FPGAs and opensource ASICs.
Together with the PCIE RootComplex project, this creates a solid foundation for flexible peripheral connectivity and high-end accelerators of video, DSP and AI workloads; all open source and community-maintained.
- The project's own website: https://github.com/chili-chips-ba/openCologne-PCIE
Run by https://intergalaktik.eu
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
