LibreSilicon: Pad Cell Generator
Custom pad cells for integrated chip layout generation
The LibreSilicon pad cell generator is the last missing puzzle piece needed for an integrated chip layout generation flow, from Design Rules and Mixed Signal designs to a layout which can be manufactured by foundries. A straightforward solution to turn the mixed signal HDL (Verilog-AMS) into a unified layout, helps to get rid of hairy IP issues when it comes to using standard cells and pad cells and other gateware from third party provider. Pad cells are used to generate the pad frame, the part of the chip around the internal logic which actually connects silicon circuits to the outside world through the pins of the package. Pad cells also protect the internal circuitry from overvoltage, overcurrent and electrostatic discharge (ESD).
- The project's own website: https://wiki.libresilicon.com/index.php?title=Pad_Cell_Generator
Run by LibreSilicon
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
