Fully Open Chip Design
Silicon-proven toolchain for VLSI design
Coriolis is an open-source toolchain dedicated to chip design. It integrates several open-source tools like Yosys, KLayout etc. and provides also dedicated tools for place & route. It addresses the actual open technologies (SkyWater, IHP and Global Foundries) to make open chips possible. The goal of this project is to improve the usability and the users' experience using Coriolis, from installing and configuring their flow to elaborating their designs. At the end, tutorials, documentation and packages will be available to make Coriolis a more usable toolchain to increase the European’s sovereignty in chips’ design and to promote open chips.
- The project's own website: https://coriolis-foundation.org
Run by Coriolis Foundation
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
