Coreblocks RISC-V processor core
Out-of-order RISC-V processor in Amaranth
Coreblocks is an experimental, modular out-of-order RISC-V core generator implemented in Amaranth (a hardware description language based on Python). It combines the Amaranth HDL with the hardware transactions library Transactron which implements an abstraction layer for inter-component interaction. This results in flexibility and low-level extensibility while preserving readable and decoupled code.
This grant will enable us to advance our generator towards synthesis of modern soft processor cores. Principally, we will overhaul the key internal modules (checkpointing, multi-stage branch prediction, LSU), allowing us to transition to high-performance processing. Next, we are going to implement processor features enabling rich OS support (MMU, FPU, supervisor mode). We will also extend our documentation in order to make this project more accessible and improve the debugging capabilities on FPGA deployments. The longer term goal of Coreblocks is to deliver a working high-performance application-class CPU, capable of supporting modern systems - an open, independent, European general-purpose processor.
- The project's own website: https://kuznia-rdzeni.org
Run by Coreforge Foundation
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
