Implement inline Verilog/VHDL through Yosys
Functional simulation in Haskell from existing Verilog/VHDL code
This project will improve integration between Clash (Haskell-based hardware design) and existing Verilog/VHDL code. It will create a pipeline that converts HDL designs into a native Haskell simulator using Yosys.
The outcome will allow developers to reuse existing Verilog/VHDL directly within Clash workflows and use Haskell’s powerful testing tools for verification — without custom build systems or external simulators. The project will lower adoption barriers, simplify verification, and strengthen the Clash ecosystem by making existing hardware designs more easily available.
- The project's own website: http://www.clash-lang.org
Run by QBayLogic
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
