Amaranth HDL
Design FPGAs and ASICs in Python
Amaranth is a hardware definition langauge for synchronous digital logic embedded within Python. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. While the language has been successfully used for many years for both FPGA projects and ASIC tapeouts, it is not yet at the "1.0" level of maturity. This grant will enable the project to ensure that all of the core abstractions are up to the same high bar of quality, as well as to bring documentation coverage to near 100%.
- The project's own website: https://amaranth-lang.org/docs/amaranth/latest/
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
