TerosHDL usability
Open source IDE for FPGA/ASIC development
TerosHDL improves the accessibility and usability of digital design workflows by providing a modern, vendor-neutral environment for working with HDL languages. It streamlines editing, simulation, FPGA interaction and project management, enabling students, researchers and professionals to work more confidently and efficiently while strengthening the broader open-hardware ecosystem. This project will deliver substantial usability and infrastructure improvements: a place-and-route manager, an FPGA loader interface based on OpenFPGALoader, and a binary manager for NVC; enhanced drag-and-drop capabilities within the project manager; frontend testing through ExTester; structured triage and resolution of existing issues; and targeted improvements to documentation, accessibility and security. The work also includes onboarding and supporting new contributors to ensure long-term sustainability and reduce the dependency on a single maintainer.
- The project's own website: https://terostechnology.github.io/terosHDLdoc/
Run by TerosHDL
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
