Timing Modeling and Integrated Verification in Naja
iming aware netlist optimisation with Logic Equivalence Checking
Naja is an open-source Electronic Design Automation (EDA) project focused on the editing, optimization, and verification of post-synthesis netlists—data structures that describe the logical connectivity of electronic circuits after synthesis.
This project will introduce two key components to Naja and the broader open hardware and EDA ecosystems: a flexible high-performance timing model engine designed for tight integration with placement and routing algorithms, and a built-in logic equivalence checking (LEC) infrastructure, optimized for incremental verification of netlist modifications—particularly in the context of Engineering Change Orders (ECOs). By addressing these important gaps in timing-aware design and incremental formal verification, the project aims to contribute important technological bricks to the open-source community, supporting the development of more capable and reliable open source EDA tools.
- The project's own website: https://github.com/najaeda/naja
Run by keplertech.io
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
