Verilog-AMS in Gnucap

Verilog-AMS is a widely used standardised modelling language for physical systems, such as electronic circuits. In this project we will continue the work on a first free/libre reference implementation. The overall goals are to improve simulation in terms of speed and feature coverage.

In this project Gnucap will implement more of the standards, specifically features related to the digital domain. New features will include the delay and signal strength modelling capabilities as well as sparse output in form of value change dumps. We will reassess and improve the performance of Verilog behavioural models and revise the mixed mode simulation algorithm. We will enhance the compatibility with Spice simulators improving the upgrade path from Spice based modelling applications. This includes the syntactical support for popular behavioural modelling devices enhancing the use of existing Spice macros within a Verilog environment. Basic scripting commands compatible with Nutmeg will be provided. We will continue the work related to data exchange between EDA tools, such as schematic and layout editors. We will extend towards compatible device representation that works across different applications enabling the seamless interchange of complete circuit models.