USB 3 PHY implementation on GateMate FPGAs
USB 3 PHY implementation with Cologne Chip GateMate FPGA Transceiver
Since its introduction at the end of the previous century, USB has developed into the most widely used interface to connect all sorts of electronic devices. Recent versions of the USB standard provide serial communication at speeds of 5Gbps and higher, which require a dedicated hardware block (transceiver) inside a chip. Throughout the last decade, FPGA devices are gaining popularity in many applications and this trend will not stop. Even small and low-cost modern FPGA devices, such as GateMate FPGA from Cologne Chip AG, include transceivers capable of communication at 5Gbps. However, no Open Hardware and FOSS implementation of USB 3.x is available. This project will enable a universal and libre USB 3.2 Gen.1 x1 (5Gbps) connectivity on the GateMate FPGA.
- The project's own website: https://www.gmm7550.dev/
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
