LIP6 VLSI Tools
Logical validation of ASIC layouts
The software we run critically depends on the trustworthiness of the chips we use. LIP6's VLSI tools are one of the few user-operated toolchains for creating ASIC layouts where the full source code is available for inspection by anyone. This provides a significant contrast to commodity chips from vendors like Intel and AMD, where anything beyond coarse technical detail is shielded away by NDA's. This project will improve Coriolis2, HITAS/YAGLE and extend the whole toolchain so that it can perform Logical Validation. It will also upgrade the code to make it faster, able to handle larger ASIC designs, and add support for lower geometries (starting with 130nm) which are more energy-friendly.
- The project's own website: https://coriolis.lip6.fr
Run by LIP6 Laboratoires Informatique Paris 6
This project was funded through the NGI Assure Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 957073.
