VACASK
High-performance Analog Simulation
VACASK (Verilog-A Circuit Analysis Kernel) is an open, high-performance analog circuit simulation platform designed to modernize the foundations of electronic design automation. By cleanly separating device modeling from numerical analysis and embracing a modular, Verilog-A centric architecture, VACASK enables efficient, extensible, and maintainable simulation workflows optimized for modern CPUs. The project introduces into VACASK essential core analyses, including AC stability, S-parameter characterization, transient noise simulation, and adjoint-based small-signal transfer function and noise evaluation, while improving numerical robustness through integration with established linear algebra libraries. Tight integration with the Python-based PyOPUS design automation library enables reproducible circuit sizing, sensitivity and yield analysis, Monte Carlo evaluation, and yield optimization workflows using VACASK as the underlying simulator.
- The project's own website: https://texlyre.org
Run by University of Ljubljana, Faculty of Electrical Engineering
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
