Calls: Send in your ideas. Deadline February 1st, 2024.
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Assisting hardware developers to deliver safer designs

TerosHDL is an open source IDE for FPGA/ASIC development. It includes a backend, a front-end built on VSCodium/VSCode and a command line interface. The goal of TerosHDL is make the ASIC/FPGA development easier and reliable: to reduce the adaptation time for new users of HW languages and help professionals.

TerosHDL is multi-platform (Linux, Windows, MacOS), multi language (VHDL, Verilog, SystemVerilog) and it takes advantages of a lot of open hardware projects (such as Edalize, WaveDrom, VUnit…), integrating them in a common graphical user interface. The IDE tries to be as much self-contained as possible and simplify the installation process.

Some of the features are: linter, go to definition, syntax highlighting, code formatting, snippets, automatic documentation, dependencies viewer, simulators support...

Run by Teros Technology

Logo NLnet: abstract logo of four people seen from above Logo NGI Assure: letterlogo shaped like a tag

This project was funded through the NGI Assure Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 957073.

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