Verilog-AMS in Gnucap (cont'd)

Verilog-AMS is a standardised modelling language widely used in analog and mixed-signal design, but without an open reference implementation. Gnucap is a modular mixed-signal circuit simulator that partially implements Verilog-AMS, that aspires to eventually implement the complete language. In 2023, with NLnet support, we made significant progress in support for Verilog-AMS, the "analog" part, also known as Verilog-A, both on the simulator side and in the model compiler. For 2024, we will extend the work, concentrating on three tasks. The first is extensions to modelgen, the model compiler, essentially completing the analog part of Verilog-AMS, with some digital. The second task is enhancements to the simulator, mostly related to fast simulation of large mixed circuits, with both analog and digital parts. The first and second tasks are related to the "mixed-signal" aspect of Verilog-AMS. The third task addresses interoperability with other software, including schematic entry and layout, ability for Gnucap to use device models from other simulators, for modelgen to generate code to be used with other simulators, and porting some analysis commands.