Hackers donate 90% of profit to charity 2019/06/13

NGI Zero awarded two EC research and innovation actions 2018/12/01

EC publishes study on Next Generation Internet 2025 2018/10/05

Bob Goudriaan successor of Marc Gauw 2017/10/12

NLnet Labs' Jaap Akkerhuis inducted in Internet Hall of Fame 2017/09/19


The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration

[The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration]

One of the key issues in a trusted, trustable ASIC is for the toolchain to be libre-licensed, so that there is no possibility for hardware-level spying or backdoor compromises. The Alliance / Coriolis2 ASIC layout toolchain by is one of the leading tools in this area. The Libre RISC-V SoC is another project being funded through NGI Zero, and at this moment that project needs to get beyond FPGA-proven status. The challenging next phase is to do an actual ASIC layout. With the System-on-Chip being developed in nmigen (a python-based HDL), Alliance / Coriolis2 also makes sense as it is written in Python as well. The funding will go towards doing an ASIC layout in 180nm.

Logo NLnet: abstract logo of four people seen from above Logo NGI Zero: letterlogo shaped like a tag

This project was funded through the NGI0 PET Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 825310. Applications are still open, you can apply today.


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Deadline February 1st, 2020.