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Webinar: Open source CPU and SoC design : The flow, the challenges and a perspective

With Charles Papon

April 11, 2024, 13:00-14:30 CEST. Watch the recording on our BigBlueButton platform.

About the webinar

While not being the first free ISA (Instruction Set Architecture), RISC-V recently made CPU design much more accessible. Consequently, in recent years, many projects emerged to develop free and open-source CPU and SoC designs.

Through the lens of the SpinalHDL, VexRiscv and NaxRiscv projects, this webinar will introduce the kind of tooling which is involved in designing a CPU and deploying it on hardware, the related challenges, the similarities and differences between hardware and software open-source, how the industry interact with open-source hardware, as well as the difficulties that the scale of such project creates.

Watch the recording & slide deck

Watch the recording on our BigBlueButton platform. Or take a look at the stand-alone slide deck.

Portrait of Charles Papon.
Charles Papon

About Charles Papon

Charles Papon graduated in 2014 with a background which mixes both hardware and software skills. His open-source hardware contributions started in 2015 with the creation of SpinalHDL, a tool made to push forward the way hardware description is done by mixing Scala and internal domain specific languages. Then, as a demonstrator of the technology, he initiated the VexRiscv project (2017, a CPU softcore). Because of its success as a CPU softcore, VexRiscv became the main SpinalHDL driver. After a few years of VexRiscv development, the need to push the boundary in the softcore space initiated the NaxRiscv project in 2021, which provided much higher performances via multi-issue and out-of-order execution capabilities as well as Debian capabilities.
His contributions to those projects were made as an individual, receiving occasional funding by either providing on site training, consultancy or feature addition.

The project SpinalHDL, VexRiscv, SaxonSoc received funding from NGI0 PET and the project NaxRiscv core improvements received funding from NGI0 Entrust , two funds established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 825322 and grant agreement No 101069594.

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