Libre-Chip Programmable Decoder
Run multiple ISAs at full speed with an open CPU
Modern computers are built on several different mutually-incompatible instruction sets such as x86, ARM, PowerISA, and RISC-V. Many of the most popular instruction sets have no high-speed libre/open-source CPUs, which makes those CPUs much harder to trust since you can't inspect their source-code to look for bugs or secret backdoors. Additionally, there are basically no existing modern CPUs which can run more than one of those ISAs without requiring software emulation, which is slow and can often be buggy. To solve those issues, this project is building a fast libre-licensed CPU that will support a programmable decoder - so the CPU can run nearly any instruction set at full speed. Another goal is to be able to prove that the resulting CPU doesn't have speculative-execution security flaws ("Spectre"-style bugs).
- The project's own website: https://libre-chip.org/
Run by Libre-Chip
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
