Dot Product Unit - DPU
Hardware accelerator for computing vector dot products
The Dot Product Unit (DPU) is an open-source hardware IP block for efficient vector dot-product computation across multiple numeric formats, including INT8, FP8, BF16, FP16, FP32 and FP64. It serves as a reusable arithmetic component for matrix-multiplication engines and related compute blocks used in AI acceleration, scientific computing, graphics, DSP and processor architectures. The design uses a pipelined SIMD datapath to process packed vector operands in parallel and reduce the products to a scalar result. It focuses on low latency, efficient hardware reuse across supported formats, and precise numerical behavior, including defined handling of rounding modes, overflow, underflow, NaNs and infinities. The project delivers synthesizable RTL, documentation, integration examples and an open verification environment with golden models, modular scoreboards, directed and random tests, functional coverage and CI support. The goal of the project is to give the open-hardware community a reusable and well-documented dot-product IP for CPUs, GPUs, vector units, DSP blocks, tensor accelerators and custom FPGA or ASIC systems.
- The project's own website: https://gitlab.com/open_chip_platform/dpu
Run by Chipfy d.o.o.
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
