CflexHDL

The C language is the premier choice for systems software, but its sequential design is often deemed ill-suited for hardware design, which relies on parallel-running blocks. While SystemC (IEEE 1666) bridges this gap, its verbosity forces a coding style that deviates from normal C. CflexHDL leverages C++20 stackless coroutines for superior performance, allowing the compiler to use CPU registers and optimize across module calls. Unlike other High-Level Synthesis (HLS) tools that automate design decisions, CflexHDL remains a true HDL offering full control including bounded clock budgets. Many such tools depend on massive proprietary codebases raising vendor lock-in, while CflexHDL's is small enough for a single developer, and still supporting critical features like pointer syntax for the full address space, arbitrary bit widths, and clean floating-point syntax.

This project will implement complex modules (e.g. a softcore CPU, raytracer), a reverse transpiler (taking SystemVerilog or other HDLs like Amaranth and compiling them back to C++), compiled-binary translator (eg. eBPF bytecode), a sandboxed SoC simulator (KVM/QEMU/Blinkenlights), and will experiment with pipelines (controlled register insertion). In addition tutorials using WASM simulation will be created.