Verilog-A Device Libraries for Open PDKs
Port Open PDKs to Verilog-A standard
Open-source PDKs are crucial in Electronic Design Automation as they make device models, design rules and data needed for design, simulation and verification, available to reproduce. But they are typically distributed in an application specific format, as so called SPICE decks - the outcomes of which depend on simulator native implementations and dialects of SPICE. This project will port device libraries to Verilog-A, the modeling language standard for analog circuits produced by the non-profit semiconductor industry consortium Accellera. Verilog-A is the continuous-time subset of Verilog-AMS. This will make PDKs easier to distribute, use, and maintain across the EDA ecosystem while reducing simulator-integration work for users and maintainers alike.
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
