uberSDIO
Add UHS-II to open hardware SD controller
This project develops a Verilog hardware RTL controller for handling SD cards from an FPGA. This controller works using the SDIO interface, and the project will add support for the UHS-II standard. This include an additional row of electrical connections on them, and feature an entirely new set of protocols: FD156, HD312, FD312, and FD624. These protocols promise throughputs of up to 624 MBytes/sec. Project outcomes include the Verilog IP, the simulation testbench, formal properties, and a hardware test to demonstrate and validate the read/wite performance of the SDIO controller on real FPGA hardware capable of implementing the both UHS-I and UHS-II hardware standards. The gateware will be deployed on a custom printed circuit board, as there are currently no FPGA boards available that provide the electrical interfaces required for these advanced SDIO standards.
- The project's own website: https://github.com/ZipCPU/sdspi
Run by Gisselqust Technology
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).
